Verification Engineer

Role Overview

The Verification Engineer will design and implement hardware verification testbenches for next-generation hardware IP. The role involves optimizing existing testbenches for enhanced performance, quality, and efficiency while contributing to the development of verification best practices.

Position Summary

This role entails specifying and developing new testbenches, improving existing ones, and implementing process improvements in hardware verification methodologies. You will work closely with cross-functional teams, including architects and software engineers, to ensure the delivery of high-quality IP components.

Experience Level

The position is targeted at candidates with demonstrable experience in hardware verification, particularly in handling complex environments and testbench architectures.

Key Responsibilities

• Evaluate design changes focusing on verification complexity.
• Develop and manage verification plans based on architecture specifications.
• Create testbenches and define coverage goals using industry-standard methods.
• Optimize verification flows and develop new scripting methods.
• Engage in collaboration with different engineering teams to define scope and goals.
• Drive high-quality IP development and ensure a robust verification process.

Essential Skills and Qualifications

• Solid background in constrained-random verification and managing complex verification environments.
• Proficient in SystemVerilog and UVM for developing reusable and scalable code.
• Strong understanding of object-oriented programming and algorithms.
• Excellent problem-solving abilities and communication skills.
• Experience in planning and estimation within projects.

Education Requirements

A degree in Electrical Engineering, Computer Science, or related field is preferred. Relevant professional experience in hardware verification is critical.