Silicon Design Engineer (ASIC/IP/SOC design verification)
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
Master's in Electrical Engineering, Computer Science, or related field with solid and independent experiences in digital ASIC/SOC or IP/SOC design verification. A good understanding of ASIC design verification flow and experience in RTL coding with Verilog/System Verilog is required. Familiarity with front-end design flow and C/C++ programming, as well as knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc. is preferred.
Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for Southbridge.
Provide the technical leadership to the DV team for the new Southbridge project.
Work independently on various DV tasks and provide technical guidance to the DV team.
Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup.
The candidate is expected to exhibit strong verbal and written communication skills in both Chinese and English, specialized knowledge, broad technical knowledge that facilitates integrative thinking, and the capability to solve complex, novel, and non-recurring problems. The ability to make critical decisions in technical areas is also required.
MSEE or BSEE with substantial independent experiences in digital ASIC/SOC or IP/SOC design verification.