Validation/Verification (UVM, Coverage, Agentic) Staff Engineer

Job Title

Validation/Verification (UVM, Coverage, Agentic) Staff Engineer

Role Summary

Staff-level verification engineer based in Hyderabad working on coverage closure for complex IP and SoC designs. The role integrates AI-assisted verification tools into existing workflows and ensures outputs are validated, debuggable, and reusable across teams.

Experience Level

Senior-level (Staff). Experience guidance: Bachelor's degree in Electronics with 2+ years of verification experience, or Master's degree in Electronics with 1+ year of verification experience.

Responsibilities

Deliver and improve verification processes, tools, and artifacts to achieve timely coverage closure.

• Drive end-to-end verification closure for IP and SoC designs including functional, code, and scenario coverage using UVM and SystemVerilog Assertions.
• Define coverage strategies, identify gaps, and prioritize verification tasks to reach signoff.
• Use AI-assisted tools to accelerate test generation and debug while independently validating all outputs for correctness.
• Collaborate with AI agents and tool teams to evaluate, refine, and benchmark generated tests, coverage analysis, and reports.
• Own the quality, tagging, and structure of verification artifacts so they are consumable by automated and AI systems.
• Pilot and measure AI-based verification solutions and report on productivity, quality, and coverage impact.
• Provide structured feedback to tool and model developers to improve accuracy and usability in verification workflows.
• Contribute to knowledge systems that enable scalable reuse of verification data across global teams.

Requirements

Required technical skills and abilities to perform the role; education items are listed separately below.

• Proven expertise in verification methodologies, including UVM, simulation practices, and SystemVerilog Assertions.
• Strong understanding of digital design fundamentals and experience with Verilog, VHDL, or SystemVerilog in SoC/IP verification contexts.
• Hands-on experience with EDA tools such as VCS and Verdi.
• Proficiency in scripting and automation (Python, TCL, or UNIX shell) for testbench and workflow integration.
• Strong debugging and analytical skills; able to diagnose corner cases and root causes across simulation and testbench layers.
• Ability to critically evaluate AI-generated outputs, identify accuracy gaps and edge cases, and provide actionable feedback.
• Experience working across distributed/global teams and communicating technical issues clearly.
• Nice-to-have: prior experience or strong interest in AI/ML-assisted verification workflows and data-driven automation.

Education Requirements

Bachelor's degree in Electronics with 2+ years of verification experience, or Master's degree in Electronics with 1+ year of verification experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.