UVM SystemVerilog Verification Engineer

Job Title

UVM SystemVerilog Verification Engineer

Role Summary

Work on verification of ASIC and FPGA designs for wireless communication systems using SystemVerilog and UVM. The role collaborates with design and development teams to validate functionality, performance, and reliability against specifications.

Primary focus is developing UVM-based testbenches, executing functional and regression tests, debugging failures, and improving verification processes and automation.

Experience Level

Senior — approximately 10 years of relevant verification experience (senior-level expectations).

Responsibilities

Typical responsibilities include designing verification environments, running tests, debugging, and reporting results.

• Develop and implement UVM-based verification plans and test strategies for FPGA and ASIC designs.
• Create SystemVerilog testbenches, test cases, and automation frameworks.
• Perform functional, system-level, and regression testing of digital hardware.
• Analyze simulation results, debug issues, and work with design engineers to resolve defects.
• Track defects and produce verification documentation and test reports.
• Optimize verification flows, tools, and test automation to improve efficiency and coverage.
• Ensure compliance with customer requirements and applicable industry standards.

Requirements

Must-have skills and experience for successful performance in this role.

• ~10 years of hands-on UVM-based verification experience for FPGA systems.
• Strong proficiency in SystemVerilog and UVM.
• Experience with simulators such as ModelSim or QuestaSim.
• Scripting proficiency (Python or Perl) for test automation.
• Experience with C/C++ for test utilities or models.
• Experience implementing bit-accurate models and debugging DSP-related designs.
• Familiarity with coverage metrics, debugging tools, and formal verification techniques.
• Knowledge of O-RAN architecture and 4G/5G protocols.
• Ability to work collaboratively in a fast-paced, cross-functional team environment.

Nice-to-have:

• Experience verifying communication protocols and hardware/software co-verification.
• FPGA development experience and knowledge of VHDL/Verilog.
• Prior design experience.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: AirSpan Networks

Headquarters: Boca Raton, Florida, United States

AirSpan Networks is a global provider of 4G and 5G network solutions, offering small cells, radios, baseband units and software for operators, enterprises and industrial applications to deliver efficient, cost‑effective connectivity.