UVM Digital Verification Engineer

Job Title

UVM Digital Verification Engineer

Role Summary

The UVM Digital Verification Engineer will develop verification strategies and testbenches for FPGA and ASIC digital designs across domains such as embedded security, cryptography, signal/image processing, navigation, and communications. The role sits on a digital design team working on block- and chip-level verification for complex mixed-signal systems.

Work includes authoring verification plans, developing UVM agents, running simulations and formal analysis, and collaborating with RTL designers to close functional and code coverage.

Experience Level

Mid-level. Typical experience: 3–5 years with a bachelor’s degree or 0–2 years with a master’s degree in a relevant field.

Responsibilities

Primary responsibilities include verification planning, testbench development, and collaboration with design teams.

• Develop verification approaches and author/execute verification plans for block and chip level.
• Design and implement UVM agents and instantiate VIPs for industry-standard buses.
• Create constrained-random tests, implement covergroups, and drive coverage closure.
• Use simulators and formal analysis tools to verify RTL; resolve simulation issues with RTL designers.
• Perform code reviews, mentor junior engineers, and document verification results.
• Contribute to system-level design trade-offs and evaluate hardware feasibility of algorithms.

Requirements

Must-have technical skills, tools experience, and program-related requirements.

• 3–5 years verification experience with a bachelor’s degree, or 0–2 years with a master’s (experience guidance retained here).
• Fluent in SystemVerilog, including SVA; recent, practical UVM/UVMF experience.
• Experience with major industry simulators (QuestaSim, Xcelium, VCS) and formal analysis tools.
• Familiarity with bus protocols (e.g. AMBA AXI) and memory interfaces (DDR3/DDR4); experience using VIPs.
• Firm grasp of constrained-random testing and coverage-driven verification; ability to achieve coverage closure.
• Scripting for verification flows (Python, Perl, Bash) and comfortable working in Linux environments.
• Strong analytical, communication, organizational, and time-management skills; experience mentoring or performing code reviews.
• Ability to work on complex multi-disciplinary projects and adapt to evolving requirements.
• Applicants must be able to obtain and maintain a U.S. government security clearance.

Education Requirements

Requires a bachelor’s degree in Engineering or a related technical field; master’s degree preferred. Relevant fields include Integrated Circuits/ASIC Hardware Engineering, Electrical/Computer Engineering, Computer Science, or other related technical disciplines.

About the Company

Company: Draper

Headquarters: Cambridge, MA, United States

Draper is an independent, nonprofit research and development organization based in Cambridge, Massachusetts. With over 2,000 employees, Draper develops advanced technologies in defense, space, biomedical engineering, and other national-security and commercial domains through multidisciplinary teams of engineers and scientists.