UCIe/D2D Post-Si Validation Engineer

Job Title

UCIe/D2D Post-Si Validation Engineer

Role Summary

Responsible for functional validation of UCIe-based die-to-die (D2D) interfaces on pre-silicon and post-silicon multi-die and chiplet SoC platforms. The role covers PHY, Adapter, protocol, sideband interfaces, link initialization/training, reliability mechanisms, power-management flows and end-to-end data transfer validation.

The engineer will develop and execute validation plans, create tests and automation, perform system bring-up and debug, and work with architecture, design, PHY, firmware, packaging, signal integrity and platform teams to close issues.

Experience Level

Mid-level (3–8 years of relevant silicon validation, high-speed interface validation, firmware-based validation, and system-level debug).

Responsibilities

Primary responsibilities focus on validation, test development, debug, and cross-team collaboration.

• Plan and perform functional validation of UCIe D2D links on pre-silicon and post-silicon platforms.
• Validate links across supported speeds (e.g., 8, 16, 24, 32 GT/s per lane), widths and package configurations.
• Develop and maintain test plans, test cases, and automation for PHY, Adapter, protocol and sideband interfaces.
• Support silicon and platform bring-up: reset sequencing, clock and PHY init, link training, and traffic enablement.
• Validate speed/width negotiation, lane mapping/reversal/disablement/repair, spare-lane usage and retraining mechanisms.
• Execute end-to-end traffic tests (register accesses, memory/DMA, streaming, cache-coherent and platform-specific traffic).
• Perform negative testing and stress scenarios (error injection, marginal channels, thermal/voltage stress, repeated retraining).
• Characterize BER, eye/timing/voltage margins, jitter tolerance, latency, bandwidth and long-duration reliability.
• Develop/debug low-level firmware, bare-metal tests and automation for init, training, traffic generation and error injection.
• Use lab equipment (oscilloscopes, BERTs, logic/protocol analyzers, JTAG) and platform telemetry to debug silicon failures.
• Document validation artifacts, track progress, report risks, and support defect triage using issue-management tools.

Requirements

Must-have technical skills and experience; nice-to-have items listed separately.

• Must-have: 3–8 years of silicon validation or high-speed interface validation experience.
• Must-have: Hands-on experience with UCIe, high-speed serial/parallel interfaces, PHY training and firmware-driven link initialization and debug.
• Must-have: Experience developing validation plans, test cases, automation scripts, and firmware or bare-metal tests for bring-up.
• Must-have: Proficiency with lab equipment and debugging tools (oscilloscopes, BERTs, logic/protocol analyzers, JTAG), and interpreting logs, traces and waveform captures.
• Must-have: Strong system-level debug skills and experience collaborating with architecture, RTL, PHY, firmware, SI, packaging and platform teams.
• Nice-to-have: Experience with protocol mappings (PCIe, CXL, streaming, raw-mode) and familiarity with reliability mechanisms (CRC, retries, replay, error reporting).
• Nice-to-have: Experience measuring BER, eye/timing margins, jitter tolerance and long-duration reliability testing.
• Nice-to-have: Experience with automation frameworks, log parsing, regression environments and improving validation infrastructure.

Education Requirements

Not specified.

About the Company

Company: Arm

Headquarters: Cambridge, United Kingdom

ARM is a global leader in semiconductor and software design, driving innovation in computing technology. The company specializes in designing processors and systems that provide the essential building blocks for electronic devices. ARM's architecture is widely used in smartphones, servers, and IoT devices, and its collaborative culture fosters bold thinking, diversity, and high-impact benefits for its talented workforce.