Turing Design Verification Senior Lead Engineer

Job Title

Turing Design Verification Senior Lead Engineer

Role Summary

Lead functional verification of complex IPs and subsystems used in next-generation SoCs. Own verification strategy, testbench architecture, and drive coverage closure from planning through sign-off.

Work closely with design, architecture, and SoC integration teams to deliver robust, reusable verification environments and ensure verification completeness across IP, subsystem, and SoC levels.

Experience Level

Senior - guideline: 4–6 years of hands-on ASIC/SoC functional verification experience.

Responsibilities

Primary responsibilities include planning and executing functional verification, building scalable environments, and driving regressions and debug to sign-off.

• Own and drive functional verification of IPs and subsystems from planning through sign-off.
• Develop verification plans, testbench architecture, and test cases from design/architecture specifications.
• Build and enhance reusable, scalable verification environments using SystemVerilog and UVM.
• Create constrained-random and directed tests, assertions, and functional coverage models.
• Drive coverage closure (code and functional) and debug failures using waveform/log analysis.
• Collaborate with design, architecture, and SoC integration teams to resolve issues and ensure verification completeness.
• Contribute to regression setup, triage, and maintenance to ensure verification quality and throughput.
• Support IP-to-subsystem-to-SoC integration and reuse of verification collateral across levels.

Requirements

Must-have technical skills and experience for this role.

• 4–6 years of hands-on ASIC/SoC functional verification experience.
• Strong proficiency in SystemVerilog and UVM methodology.
• Proven experience in IP, subsystem, and/or SoC-level verification.
• Solid understanding of constrained-random stimulus, functional coverage, assertions (SVA), and scoreboarding.
• Strong debug skills using simulation logs and waveform tools (for example, Verdi/FSDB).
• Good understanding of digital design fundamentals, bus protocols, and SoC architecture.
• Proficiency in scripting (Python, Perl, Tcl) for automation and flow development.
• Strong analytical, problem-solving, and communication skills.

Nice-to-have:

• Experience with low-power verification (UPF / power-aware flows).
• Exposure to gate-level simulation (GLS) including timing and SDF-based verification.
• Familiarity with formal verification, emulation, or performance verification.
• Experience with industry-standard bus protocols (AXI, AHB, APB).

Education Requirements

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field (with 3+ years relevant experience) OR Master's in the same fields (with 2+ years) OR PhD in the same fields (with 1+ year). Equivalent practical experience is acceptable.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.