Top-Level Physical Design Engineer
TenstorrentJob Title
Top-Level Physical Design Engineer
Role Summary
Senior physical design engineer responsible for full-chip implementation and closure of complex AI/CPU SoC designs. The role drives hierarchical floorplanning, power-grid and clock-network implementation, signoff analysis, and cross-functional coordination with architecture, RTL, packaging, and verification teams.
This position is hybrid, based out of Austin, TX; Santa Clara, CA; or Fort Collins, CO.
Experience Level
Senior-level. Prefer candidates with 8+ years of top-level SoC physical design experience.
Responsibilities
Primary responsibilities at the chip level:
- Lead top-level floorplanning and hierarchical physical implementation for multi-million-gate SoCs.
- Design and implement power delivery networks, multi-voltage domain planning, and bump/RDL strategies.
- Define and implement global clock distribution and timing closure strategies across the chip.
- Perform EM/IR analysis, physical verification, and interface with signoff teams to achieve chip-level closure.
- Coordinate cross-discipline tradeoffs with architecture, RTL, packaging, and verification groups to meet PPA targets and schedules.
- Drive implementation reviews, document constraints and floorplans, and enforce physical design quality and manufacturability.
- Mentor and guide other engineers on top-level physical-design best practices and methodologies.
Requirements
Must-have technical qualifications and constraints:
- 8+ years of top-level SoC physical design experience on complex, multi-million-gate chips.
- Deep expertise in hierarchical floorplanning, fabric implementation, power grid design, and global clock distribution.
- Proven experience with bump planning, RDL implementation, and multi-voltage domain designs.
- Strong track record in timing closure, EM/IR analysis, and physical verification at the chip level.
- Proven ability to drive cross-functional collaboration and deliver chip-level closure on aggressive schedules.
- Employment contingent on eligibility to access U.S. export-controlled technology (may require U.S. citizenship, permanent residency, or an approved export license).
Nice-to-have:
- Experience with chiplet integration, advanced packaging co-design, or AI accelerator/CPU SoC projects.
- Experience mentoring teams and establishing top-level physical-design processes at scale.
Education Requirements
Not specified.
About the Company
Company: Tenstorrent
Headquarters: Austin, Texas, United States
Tenstorrent is a technology company focused on designing innovative computing solutions. They are known for their expertise in the development of advanced hardware, including ASICs and SoCs, aimed at enhancing performance and efficiency in various applications.
