Timing & Power Analysis CAD Engineer

Job Title

Timing & Power Analysis CAD Engineer

Role Summary

Member of Marvell Central Engineering CAD team responsible for developing and maintaining timing and power signoff flows and automation within the M1DP CAD platform. The role supports physical design and front-end teams to enable timing- and power-aware optimization across ASIC projects.

Experience Level

Mid-level engineer. Role requests 6 to 10 years of hands-on experience in CAD flow development or power analysis in the semiconductor industry.

Responsibilities

Key responsibilities include developing, validating, and supporting timing and power analysis flows and automation, and delivering actionable reports to design teams.

• Develop, maintain, and enhance PrimeTime-STA and PrimePower-based power signoff flows within the M1DP CAD platform.
• Implement and support in-design timing and power flows for timing/power-aware optimization during physical implementation.
• Collaborate with Physical Design and Front-End teams to prepare FSDB/activity files, UPF/CLP power intent, and SAIF/vector annotation.
• Create and maintain automation scripts (Tcl, Python) for flow execution, debugging, and reporting.
• Generate, validate, and deliver power analysis reports (dynamic, leakage, glitch) and build power dashboards for multiple ASIC projects.
• Support tapeout activities to ensure power and timing signoff closure across blocks and full-chip designs.
• Interface with EDA vendors to evaluate tool features, report bugs, and drive improvements.
• Document flows and train global teams on timing and power CAD processes.

Requirements

Must-have technical skills and qualifications for daily execution. Nice-to-have items are noted.

• Proven experience with Synopsys PrimeTime and PrimePower (gate-level and/or RTL-level power analysis).
• Strong understanding of static timing analysis (STA) flows, including hierarchical designs and timing QoR correlation between P&R and signoff engines.
• Solid understanding of power analysis concepts: dynamic power, leakage, glitch power, and clock gating efficiency.
• Experience with FSDB, VCD, SAIF activity file generation and annotation flows.
• Familiarity with UPF/CPF power intent and multi-voltage design methodologies.
• Proficiency in Tcl scripting for CAD flow development and automation; Python experience for reporting/automation is expected.
• Working knowledge of Physical Design (P&R) flows and their interaction with timing and power signoff.
• Strong analytical and debugging skills; effective verbal and written communication for collaboration with global teams.
• Must be eligible to access export-controlled technology as required by applicable law (export license review may apply).
• Nice-to-have: experience with PrimePower RTL 2.0 adoption, glitch analysis/optimization flows, and use of Hyperscale & Context models for hierarchical STA.

Education Requirements

B.E./B.Tech or M.E./M.Tech in Electrical Engineering, Electronics Engineering, Computer Science, or a related technical field.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.