Timing Design (STA) Leader for Automotive SoC Design
RenesasRole Summary
The Timing Design (STA) Leader for Automotive SoC Design at Renesas will be responsible for establishing the overall strategy for SoC timing design, focusing on static timing analysis (STA). This role demands close cooperation with global teams, particularly in India and Vietnam, to integrate various cutting-edge technologies into automotive SoCs.
Experience Level
Mid-level, with substantial experience in timing design.
Responsibilities
Key responsibilities include:
- Establishing the overall strategy for SoC timing design (Static Timing Analysis: STA).
- Developing and performing quality checks of SDC (timing constraints).
- Evaluating and driving the introduction of new tools and design flows.
Requirements
Candidates must possess the following qualifications:
- Experience in timing design and LSI design using logic synthesis tools.
- Experience in creating SDCs and performing SDC quality checks using timing analysis tools.
- Development experience using scripting languages such as Python and Tcl.
- English communication skills.
Additionally, the following qualifications are preferred:
- Experience with scripting languages, notably Python.
- Knowledge of major SoC IPs such as CPU, GPU, image processing IPs, buses, and memory controllers.
Education Requirements
Not specified.
About the Company
Company: Renesas
Headquarters: Hitachinaka, Japan
Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.
