Tessent Technology Enablement Engineer (IJTAG)

Role Overview

A Tessent Technology Enablement Engineer is required to work on developing and enhancing Electronic Design Automation (EDA) tools specifically focusing on IJTAG and related standards. The role involves deep technical engagement with IEEE standards and DFT methodologies to support the integration and application of these advanced technologies.

Experience Level

This position typically requires three to five years of relevant experience and a bachelor's degree in computer science, engineering, or a related field.

Key Responsibilities

The engineer will be responsible for:

• Mastering and applying IEEE 1149.1 (JTAG standard) for boundary scan pattern generation and debugging.
• Utilizing IEEE 1687 (IJTAG standard) to interpret ICL and PDL, facilitating embedded test and debug integration.
• Understanding and applying IEEE 1838 standards in multi-die designs.
• Engaging with DFT design and verification fundamentals, including scan design and memory BIST.
• Leveraging DFT tools for integrating JTAG/IJTAG implementations and performing validation.
• Effectively communicating complex technical concepts to team members and stakeholders.

Required Skills and Qualifications

The following skills and abilities are essential for this position:

• In-depth knowledge of IEEE standards relevant to JTAG and IJTAG.
• Proficient in reading and understanding RTL code.
• Strong problem-solving and analytical skills.
• Excellent written and verbal communication capabilities.
• Ability to work effectively in a team-oriented environment.

Education Requirements

A bachelor's degree in computer science, engineering, or a related discipline is required.