Technical Staff Engineer - Verification

Job Title

Technical Staff Engineer - Verification

Role Summary

Senior verification engineer on the FPGA Business Unit team responsible for functional verification of next-generation, secure, low-power FPGA and SoC products. The role focuses on developing reusable UVM testbenches, formal and C-based verification flows, and collaborating with architecture, emulation, and prototyping teams to achieve first-silicon success.

Experience Level

Senior-level. The posting requests very experienced candidates (approximately 12+ years; specific listing cites 12.5+ years in functional verification).

Responsibilities

Primary responsibilities include planning and executing verification for complex SoC/subsystems and mentoring others.

• Develop and maintain reusable UVM-based testbenches and verification environments.
• Perform functional, power-aware and gate-level verification using constrained-random, formal, and C-based methods.
• Integrate AI/ML-enabled verification methods to improve quality and productivity.
• Collaborate with emulation, hardware prototyping, and architecture teams to define unified verification methodologies and ensure first-silicon success.
• Support emulation and FPGA-accelerated simulation flows and post-silicon debug activities.
• Mentor and guide junior verification engineers.

Requirements

Must-have technical skills and tools; preferred items listed separately.

• Extensive experience (12+ years) in functional verification of complex SoC designs.
• Expertise in SystemVerilog, UVM, and formal verification methodologies.
• Proven experience in verification methodology development and tool automation.
• Familiarity with AI/ML-driven EDA tools and scripting for flow integration.
• Good understanding of SoC architectures (ARM, RISC-V).
• Experience with at least two of these domains: CPU subsystems; PCIe Gen3/4/5; DDR4/DDR5/LPDDR4X; MIPI DSI/CSI; Ethernet MAC; USB; security/cryptography IPs.
• Exposure to emulation, hardware prototyping and post-silicon debug; experience with FPGA-based acceleration platforms.
• Proficiency in scripting and automation: Python, TCL/TK, C/C++.
• Familiarity with verification tool suites (Siemens/Cadence/Synopsys) and revision control systems (Git, Perforce, SVN).
• Strong debugging skills and experience working with global cross-functional teams; effective communication and collaboration.

Nice-to-have:

• Strong understanding of FPGA architecture.
• Experience with coverage-driven verification using ML-based optimizations.
• Knowledge of complete SoC RTL-to-GDS-to-silicon release flows.

Education Requirements

Required: BS or MS in Electrical/Electronic Engineering. The posting specifies this academic requirement together with extensive experience (the listing also references ~12+ years of relevant verification experience).

About the Company

Company: Microchip

Headquarters: Chandler, Arizona, USA

Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.