Technical Staff Engineer - Physical Design

Job Title

Technical Staff Engineer - Physical Design

Role Summary

Responsible for implementing and optimizing ASIC/SoC physical design from RTL to signoff, including floorplanning, placement, routing, timing closure, and physical verification. Works within a multi-discipline design team to translate logic designs into manufacturable layouts that meet performance, area, and power targets.

Collaborates with synthesis, timing, verification, DFT, and layout teams to resolve issues, automate flows, and support production tapeout activities.

Experience Level

Mid-level. Specific years of experience not specified in the source posting.

Responsibilities

Core responsibilities include implementing physical design tasks, debugging issues, and supporting signoff and production activities.

• Perform physical implementation tasks: floorplanning, placement, clock-tree synthesis (CTS), routing, and ECO insertion.
• Work on static timing analysis and timing closure; collaborate with RTL and STA engineers to meet timing constraints.
• Prepare designs for physical verification and signoff (DRC/LVS/MR) with foundry tool flows.
• Develop and maintain scripts and automation for tool flows (e.g., Tcl, Python, shell).
• Diagnose and resolve physical-level issues, support ECOs, and participate in tapeout readiness reviews.
• Coordinate with cross-functional teams (verification, DFT, manufacturing) to ensure design manufacturability and yield.

Requirements

Must-have technical skills and desirable additional qualifications.

• Must-have: Practical experience with ASIC/SoC physical implementation and signoff flows; familiarity with EDA physical-design and verification tools.
• Must-have: Scripting ability for flow automation (Tcl, Python, or shell) and experience working in Linux environments.
• Must-have: Knowledge of static timing analysis, timing closure techniques, and physical verification concepts (DRC/LVS).
• Nice-to-have: Experience with specific tools (e.g., Cadence Innovus, Synopsys ICC2, Mentor Calibre), advanced process nodes, low-power or multi-voltage design, and DFT considerations.
• Nice-to-have: Prior tapeout experience and demonstrated ability to collaborate across engineering teams.

Education Requirements

Not specified.

About the Company

Company: Microchip

Headquarters: Chandler, Arizona, USA

Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.