Technical Program Manager, Silicon/Hardware

Job Title

Technical Program Manager, Silicon/Hardware

Role Summary

The Technical Program Manager will own cross-functional execution for advanced silicon and hardware programs from early planning through tapeout. You will coordinate Architecture, RTL, Design Verification, packaging, test, and supply-chain stakeholders to deliver performant, manufacturable SoC/chiplet products.

This role sits on the Hardware team and focuses on schedule governance, risk mitigation, stage-gate reviews, and tapeout readiness for GenAI-focused silicon.

Experience Level

Senior - requires 15+ years in chip/IC development with at least 3 years in a technical program manager role.

Responsibilities

Own program execution and the operational framework for silicon HW projects. Key responsibilities include:

• Lead end-to-end execution of silicon hardware programs from concept through production.
• Drive planning, milestones, stage-gate reviews, and transitions from architecture into implementation and verification.
• Partner with Architecture, RTL, and DV teams to identify bottlenecks, track coverage metrics, and close verification gaps.
• Track technical dependencies, critical path, schedule risks, owners, and closure dates.
• Manage risks related to design maturity, IP readiness, verification closure, physical signoff, package/test readiness, and supply chain.
• Develop program-management playbooks, best practices, and escalation paths for the HW organization.
• Provide clear, timely executive-level updates and act as liaison between hardware teams and leadership.

Requirements

Must-have:

• 15+ years of chip/IC development experience (engineer, engineering manager, or TPM) with ≥3 years in a technical program manager role.
• Proven experience leading silicon HW programs through multiple lifecycle phases (concept to silicon/tapeout).
• Technical fluency in SoC or chiplet design flows, RTL milestones, DV signoff, and silicon bring-up phases.
• Strong technical judgment managing tradeoffs across performance, power, area, cost, schedule, quality, and risk.
• Experience driving schedules, dependency management, issue tracking, risk mitigation, milestone governance, and executive communication.
• Proficiency with program-management and engineering collaboration tools (Jira, GitHub, Confluence, Smartsheet, MS Project, Google Workspace, or equivalent).
• Excellent written and verbal communication; able to summarize technical risks and schedule impact.
• Must be authorized to work in the United States and able to work from the Mountain View office Tuesdays–Thursdays.

Nice-to-have:

• Experience with AI infrastructure, datacenter racks, networking, storage systems, or high-power server platforms.
• Experience with high-speed interconnects, liquid-cooled systems, telemetry, diagnostics, or rack-scale validation.
• Prior hands-on engineering experience in back-end physical design (BE PD).

Education Requirements

Not specified.

About the Company

Company: MatX

Headquarters: Mountain View, California, USA

MatX specializes in creating faster chips for large language models (LLMs), focusing on innovative hardware and software solutions. The company fosters a collaborative and supportive work environment, welcoming candidates of all experience levels. Their approach prioritizes deep understanding and consideration of novel methods to drive efficiency and performance in their projects, particularly in silicon design and related engineering roles.