Technical Lead – Physical Design (RTL to GDSII)

Job Title

Technical Lead – Physical Design (RTL to GDSII)

Role Summary

Lead and own end-to-end RTL-to-GDSII implementation for complex IP/SoC subsystems and build a backend physical-design team. Define the RTL-to-GDS methodology, constraints, sign-off criteria and delivery metrics, and collaborate with RTL, full-custom layout and integration teams.

This is a hands-on technical leadership role: you will both set the flow and personally de-risk and own the most challenging implementation tasks.

Experience Level

Senior — typically 10+ years in ASIC physical design with responsibility as block/subsystem owner; 2+ tapeouts expected.

Responsibilities

Primary responsibilities include establishing and executing the RTL-to-GDSII flow and building a capable backend team.

• Define and maintain RTL-to-GDS flow: constraint strategy, libraries/PDKs, UPF/CPF, and sign-off checks.
• Perform synthesis, floorplanning, partitioning, place & route, clock-tree synthesis, routing, extraction, and closure to sign-off.
• Set predictable PPA targets, lead timing and power ECOs, and correlate pre/post-layout timing.
• Integrate custom macros, SRAMs, I/O, manage clocking strategy, CDC, and hard-macro/LEF hierarchical integration.
• Own low-power intent (UPF/CPF), isolation/retention strategies, level shifting, and power-aware STA/simulation.
• Ensure DFT and test hooks are preserved in implementation (scan/MBIST coordination, test timing).
• Automate and industrialize the flow with Tcl/Python, reproducible configs, CI/CD, and metrics dashboards.
• Recruit, develop, and scale a 5+ engineer backend team with clear ownership areas and sign-off standards.
• Interface with foundries on PDK updates, waivers, rules (antenna/density), and reliability guidance.

Requirements

Must-have technical skills and experience.

• 10+ years in ASIC physical design; 2+ successful tapeouts as block/subsystem owner (synthesis to sign-off).
• Deep expertise in a complete EDA toolchain (Synopsys or Cadence).
• Hands-on power-optimization experience, including activity-based power correlation (VCD/SAIF) and glitch reduction.
• Strong MCMM STA and timing-closure experience; proven ECO execution.
• Experience in floorplanning, partitioning, hierarchical integration, grid planning, and IR/EM analysis and fixes.
• Practical UPF/CPF experience for multi-voltage, power-gated designs, including power-aware STA and simulation.
• Scripting and automation proficiency (Tcl, Python) and version control (Git, Perforce, or similar).
• Ability to lead independently, make major technical decisions, and own delivery risk.

Nice-to-have:

• DFT exposure (scan planning, test timing, MBIST) and formal equivalence workflows.
• Package/board co-design awareness (bump/rail planning, SSO/PI, thermal assumptions).
• Experience at advanced nodes (≤7 nm) with multi-patterning/EUV and variability considerations.
• Familiarity with sign-off requirements for safety-/quality-critical markets and waiver governance.

Education Requirements

Not specified.

About the Company

Company: Synthara

Headquarters: Zürich, Switzerland

Synthara develops ComputeRAM® hardware and software for efficient on-device AI, providing compilers, drivers, SDKs and tooling to enable AI workloads from microcontrollers to accelerators, with a focus on hardware/software co-design and developer usability.