System Performance Modeling Engineer

Job Title

System Performance Modeling Engineer

Role Summary

Work on platform infrastructure architecture and performance for Qualcomm SoCs within the Infrastructure IP Team, with an emphasis on NoC topology and system memory architecture. The role performs architecture-oriented performance and power studies using cycle-accurate and higher-level models, develops modeling tools, and partners with IP designers and system architects to guide SoC decisions.

Experience Level

Mid-level. Preferably 2–5 years of relevant SoC modeling and/or software development experience; new graduates with strong internships and motivation will be considered.

Responsibilities

Conduct system- and IP-level performance and power analyses, develop modeling tools, and collaborate with architects and design teams.

• Lead NoC topology and system memory architecture exploration campaigns and analyze results to inform SoC requirements.
• Drive performance and power explorations across platform components: NoC, memory subsystem, system cache, and memory controllers.
• Develop, expand, and maintain modeling frameworks and validation/exploration tools (primarily performance and power focused).
• Define experiments, run simulations (cycle-accurate and approximate), and extract actionable insights from complex datasets.
• Support exploratory methodology work involving data science and machine learning techniques.
• Document modeling frameworks and participate in defining hardware modeling semantics.
• Collaborate with IP designers, system architects, and performance teams to influence architecture decisions.

Requirements

Must-have technical skills, practical experience, and communication abilities. Preferred items listed as "nice-to-have."

• Strong understanding of computer architecture, memory hierarchy, and system/platform architecture.
• Knowledge of NoC concepts, topologies, and design trade-offs.
• Proficiency in Object-Oriented Programming (C++ and Python).
• Familiarity with interconnect/bus protocols and micro-architecture (AHB/AXI/ACE/ACE-Lite and similar).
• Experience with performance, power, and area trade-off analysis and simulation-driven studies.
• Ability to analyze complex datasets and communicate findings to technical stakeholders.
• Experience or interest in data science and machine learning methods applied to modeling or analysis.
• Adaptability to changing priorities and strong written and verbal communication skills.
• Nice-to-have: experience driving architecture-level performance/power investigations on IP blocks (CPU, GPU, multimedia, memory controller, system cache) and familiarity with LPDDR/DDR protocols.

Education Requirements

Degrees: Bachelor's, Master's, or PhD in Microelectronics, Computer Science, Science, Engineering, or a related technical field. Typical qualification combinations listed by the employer: Bachelor's + 2+ years of ASIC-related experience; Master's + 1+ year; or PhD. New graduates with strong internships may be considered.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.