System Modelling Engineer

Job Title

System Modelling Engineer

Role Summary

The role leads architecture, system-level modeling and performance analysis for high-speed SerDes PHYs (224 Gbps), covering transmitter, channel and receiver behavior, equalization, clocking, and jitter/noise analysis. The position supports architecture decisions, compliance interpretation, and silicon bring-up for ASICs and SoCs within Intel's Central Engineering Group.

Work is focused on building behavioral, statistical and time-domain system models to drive robust silicon implementation and validation across electrical channels, packages and PCBs.

Experience Level

Senior-level. Experience guidance: Bachelor's degree +12 years, Master's degree +8 years, or PhD +4 years of relevant experience.

Responsibilities

Primary responsibilities include system architecture, modeling, analysis, and cross-functional alignment to deliver reliable high-speed links.

• Develop end-to-end behavioral and time-domain models for 224 Gbps SerDes PHYs across TX, channel, and RX.
• Build statistical models to evaluate BER, eye margins, and link robustness under worst-case conditions.
• Define PHY performance budgets (jitter, noise, ISI, crosstalk, insertion loss) and translate system requirements into block- and circuit-level specs.
• Model and optimize PAM4 signaling at very high data rates and tune TX FIR, RX CTLE, DFE, and adaptive equalization algorithms.
• Model electrical channels including packages, PCBs, connectors, and crosstalk; perform swept-channel analysis and support co-optimization of channel, package, and PHY architecture.
• Model PLL/DLL behavior, phase noise and jitter transfer; perform jitter decomposition and bathtub analysis; analyze CDR performance and loop dynamics.
• Support standards- and compliance-related modeling (IEEE, OIF, etc.) and define channel/compliance test methodologies aligned to silicon validation.
• Collaborate with circuit designers, DSP/algorithm teams, package/PCB engineers, and validation teams; correlate lab data with system models to support silicon bring-up and debug.

Requirements

Concise list of required technical capabilities and desirable additional skills.

• Must-have: Proficiency in analog circuit concepts for TX/RX blocks and system-level understanding; expertise in architecture modeling and high-speed SerDes design techniques.
• Must-have: Demonstrated ability to model, simulate, and optimize performance (BER, eye), power, and area for analog and mixed-signal IPs; experience with channel modeling and equalization algorithms for PAM4 links.
• Must-have: Experience with jitter/noise analysis, PLL/CDR behavior, jitter decomposition (RJ/DJ/PJ/SJ) and bathtub analysis.
• Must-have: Experience defining PHY performance budgets and translating system requirements into lower-level specifications; hands-on correlation of models with lab/silicon data.
• Nice-to-have: Experience influencing cross-functional roadmaps, leadership in IP architecture, and familiarity with industry standards (IEEE, OIF) related to 224G efforts.
• Nice-to-have: Strong written and verbal communication skills for presenting architectural trade-offs to stakeholders.

Education Requirements

Minimum qualifications specify a Bachelor's degree in Electrical Engineering, Computer Engineering, or a related specialized field (with 12+ years relevant experience), or a Master's degree (with 8+ years), or a PhD (with 4+ years). The posting allows equivalent relevant experience in place of the degree-based experience thresholds. No specific certifications were listed.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.