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System & FPGA Platform Engineer

Epic ASIC
September 25, 2026
Full-time
On-site
Toronto, Ontario, Canada
$120,000 - $140,000 CAD yearly
FPGA Programming Jobs, Level - Senior

Job Title

System & FPGA Platform Engineer

Role Summary

Lead FPGA prototyping and system-level platform engineering from architecture through working system. Own multi-FPGA prototype development, RTL partitioning to FPGA, board and rack-level requirements, and silicon bring-up activities in collaboration with software and firmware teams.

Experience Level

Senior - typically requires 7+ years of experience in FPGA prototyping, system/board design, or silicon bring-up.

Responsibilities

Primary responsibilities include building and validating FPGA prototypes, defining system requirements, and driving bring-up and debug activities.

  • Build and maintain multi-FPGA prototype platforms (e.g., AMD Versal/Alveo class) including HBM and PAM4 transceivers; maintain a Toronto-hosted lab rig.
  • Port and partition RTL to FPGA; perform timing closure, transceiver bring-up, PCIe host link bring-up, and implement debug infrastructure.
  • Define system-level requirements: host interface, board design, power/thermal budgets, clocking and synchronization across accelerators.
  • Create bring-up plans and lab validation procedures for first silicon.
  • Work with software and firmware teams on drivers, firmware integration, and demo workloads.

Requirements

Must-have technical skills and practical lab experience.

Must-have:

  • Strong experience with Vivado and Versal flows, and FPGA prototyping toolchains.
  • Expertise with multi-gigabit transceivers and PCIe endpoint design.
  • Hands-on lab debugging: oscilloscopes, BERT, protocol analyzers; methodical hardware debug practices.
  • Scripting in Python and Tcl; basic Linux driver-level familiarity.
  • Experience with timing closure and transceiver bring-up.

Nice-to-have:

  • Rack-scale or multi-accelerator system design experience (GPU servers, switch systems).
  • Signal integrity / power integrity awareness for 32G NRZ / 64G PAM4 links.
  • Post-silicon validation experience with GPU, NPU, or networking ASICs.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering (BS/MS EE or CE) as specified in the source posting.


About the Company

Company: Epic ASIC

Headquarters: Toronto, Ontario, Canada

Toronto-based semiconductor design company providing end-to-end ASIC and SoC development services from architecture and RTL through tapeout and production. Works on high-performance computing, custom ASICs, high-bandwidth data movement, power optimization, and hardware for AI/datacenter infrastructure.

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Date Posted: 2026-09-24