Synthesis STA Expert

Role Summary

This position involves working with the NBIO IP Physical aware group to contribute to innovative designs at AMD. The role is focused on synthesizing complex and high-speed IPs while ensuring the best performance and power-area efficiency (PPA) in collaboration with various engineering teams.

Experience Level

Candidates should possess over 15 years of experience in the synthesis, STA, and LEC domain, demonstrating expertise in physical design and synthesis cycle.

Responsibilities

• Synthesize complex IPs and develop constraints.
• Utilize and manage hands-on expertise in Synthesis and Static Timing Analysis (STA).
• Execute conformal flow and Logic Equivalence Check (LEC).
• Collaborate with the RTL team to implement adjustments in microarchitecture driven by physical requirements.
• Coordinate among multiple System on Chip (SoC) projects for complex IPs.
• Engage in physical design activities including floor planning, placement, clock tree synthesis, and routing.
• Lead and mentor junior team members in technical areas.

Requirements

Expected qualifications include a strong understanding of physical design, STA, and experience with the design cycle. Excellent problem-solving skills, detail orientation, and effective communication are crucial for success in this role.

Education Requirements

A Bachelor's or Master's degree in Computer Engineering or Electrical Engineering is required.