Synthesis-DFT Stitch CAD Engineer
QualcommJob Title
Synthesis-DFT Stitch CAD Engineer
Role Summary
Member of Qualcomm's Global CAD team working on gate-level synthesis and DFT-stitch implementation tools and methodologies for Snapdragon SoCs. The role develops and maintains implementation flows to improve performance, power, area (PPA) and cycle time, and collaborates with Snapdragon design teams and EDA vendors to deliver production-ready solutions.
Experience Level
Mid-level. Typical experience 5–10 years in VLSI CAD or implementation-related roles; minimum qualifications in the posting tie required years to degree level (see Education Requirements).
Responsibilities
Primary responsibilities include:
- Develop and maintain Qualcomm's DFT-stitch flows and synthesis methodologies using Synopsys/Cadence tools and internal tools.
- Improve SoC synthesis and DFT-stitch methods for mobile, compute, AI, and IoT Snapdragon products.
- Enable and validate new EDA or internal tool features for synthesis and DFT checks; drive vendor enablement.
- Develop methodology to handle complex multi-voltage crossings on DFT paths.
- Support Snapdragon design teams via ticket queues and technical troubleshooting (e.g., cell legalization, congestion, DFT stitch failures).
- Set up and maintain regressions of complex DFT-stitch and synthesis testcases.
- Innovate flow and tool techniques for area and dynamic power reduction and faster turn-around time; contribute to R&D and patentable ideas.
Requirements
Must-have skills and experience:
- Hands-on experience with synthesis, DFT-stitch, and place-and-route implementation flows.
- Experience developing CAD methodologies and integration of EDA tool flows (vendor interaction and enablement).
- Strong scripting and programming skills (Python and TCL preferred).
- Experience debugging implementation issues such as congestion, cell legalization, and DFT failures.
- Experience setting up and maintaining regressions and complex testcases for implementation flows.
- Ability to collaborate with internal design teams and external EDA vendor application engineers.
Nice-to-have: exposure to genAI/ML techniques applied to implementation, experience with advanced foundry process nodes, and prior participation in patentable R&D.
Education Requirements
Bachelor's, Master's, or PhD in Computer Engineering, Electrical Engineering, Science, Engineering, or a related technical field. The posting specifies degree-linked minimum experience: Bachelor +6+ years, Master +5+ years, or PhD +4+ years of ASIC design, verification, validation, integration, or related experience.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
