SW Engineering Manager – Performance Modeling
SpeedataJob Title
SW Engineering Manager – Performance Modeling
Role Summary
Lead the Simulators Team to design and deliver functional and performance hardware simulators used for architectural exploration, compiler optimization and system-level verification for a purpose-built analytics SoC.
The role requires close collaboration with Architecture, VLSI and Software teams to influence chip architecture, tooling and system performance.
Experience Level
Senior — requires significant technical leadership and team management experience. The posting requests 3+ years managing or leading software teams and 5+ years developing hardware simulators.
Responsibilities
Lead the team that builds and maintains the simulator suite and supporting tools.
- Manage and grow a team of software engineers focused on hardware simulation and performance modeling.
- Design, develop and evolve functional and performance simulators for SoC cores.
- Collaborate with Architecture, VLSI and Software teams on SW–HW co-design initiatives.
- Provide performance insights to influence chip architecture, compiler optimizations and system-level behavior.
- Develop tools that accelerate the chip development and validation cycle.
Requirements
Key must-have skills and experience.
- Must-have: 3+ years managing or leading software engineering teams.
- Must-have: 5+ years developing hardware simulators and strong understanding of computer architecture and system-level modeling.
- Must-have: Proven technical leadership in SW–HW co-development environments.
- Must-have: Proficiency in Python and C++.
- Must-have: Solid software engineering practices: design, testing, performance tuning and maintainability.
Education Requirements
BSc (or higher) in Computer Science, Mathematics, Physics or Electrical Engineering.
About the Company
Company: Speedata
Speedata develops a purpose-built ASIC, the Analytics Processing Unit (APU), to accelerate analytics and AI data workloads (e.g., Apache Spark), improving query performance and reducing infrastructure TCO by executing analytics operations in silicon.
