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Substrate Packaging Defect Metrology Tool Owner

Intel Corporation
May 05, 2026
Full-time
On-site
Phoenix, Arizona, United States
$103,730 - $198,820 USD yearly
Test Engineering Jobs, Level - Senior

Job Title

Substrate Packaging Defect Metrology Tool Owner

Role Summary

Defect Metrology Engineer responsible for ownership and deployment of defect inspection/metrology tools for substrate and advanced packaging programs. The role partners with yield, process integration, module teams, suppliers and factory teams to detect and resolve defects, qualify tools, and enable high-yield substrate packaging production.

The position sits on the SPTD Yield team and focuses on EMIB-T, glass core, EMIB scaling, and panel-level packaging technologies across substrate and assembly/test manufacturing.

Experience Level

Senior level — requires multiple years of industry experience consistent with senior technical ownership and project leadership (see Education Requirements for specific degree + experience combinations).

Responsibilities

Primary responsibilities include hands-on tool ownership, data-driven yield improvement, and cross-functional coordination to meet program deliverables.

  • Operate and own defect inspection/metrology tools to detect and resolve process issues and improve yield.
  • Analyze real-time data, produce reports and DOE summaries to guide process and equipment improvements.
  • Lead next-generation tool installations and milestones (purchase spec, source inspection, design, pre-fac, safety approvals, supplier qualification, Intel qualification).
  • Develop and deploy procedures, equipment setups, and data flows; connect new tools to automation and yield-analysis systems.
  • Collaborate with equipment suppliers and supply‑chain partners to maintain and enhance tool capabilities (software/hardware upgrades).
  • Maintain WIP velocity targets with factory teams and module partners; support defect reduction and yield enhancement initiatives.
  • Prepare and present tool/system capability roadmaps and status to leadership; demonstrate independent problem-solving and leadership in a fast-paced environment.

Requirements

Must-have technical experience and skills. Degree and field requirements are listed separately under Education Requirements.

  • Several years of experience in semiconductor manufacturing with responsibility for yield or defect reduction and prior defect metrology tool ownership.
  • Practical experience with defect inspection tools, equipment troubleshooting, and tool qualification processes.
  • Experience applying data analysis and experimental design (DOE) to guide process or tool improvements.
  • Ability to manage projects independently and coordinate cross-functional stakeholders during tool installation and qualification.
  • Experience setting up data flows, connecting tools to automation and yield-analysis systems, and ensuring reliable data collection.
  • Strong communication skills for presenting technical status and capability to leadership and partners.
  • Willingness and ability to work on-site as required by the role.

Education Requirements

Bachelor's degree in Electrical Engineering, Chemical Engineering, Mechanical Engineering, Optical Engineering, Materials Science, Physics, or a related field with 6+ years' experience; OR Master's degree in those fields with 2+ years' experience; OR PhD in those fields with 1+ years' experience. Requirements may also be met through a combination of industry experience, internships, and relevant coursework/research.


About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.

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Date Posted: 2026-05-05