Substrate IC Package Layout Design Engineer

Job Title

Substrate IC Package Layout Design Engineer

Role Summary

Responsible for end-to-end layout design of large, high-power, high-speed IC substrate packages for AI processors and accelerators. Collaborates with silicon, SI/PI, packaging, and manufacturing teams and OSAT partners to deliver manufacturable substrates optimized for power delivery, signal integrity, and thermal performance.

Experience Level

Senior — 10+ years of experience in IC substrate layout design for high-performance processors or accelerators.

Responsibilities

Design, verify, and document multi-layer substrate packages; collaborate with cross-functional teams.

• Lead layout design for large (>50mm) multi-layer IC substrates with high pin counts and dense routing.
• Develop power delivery network layouts capable of supporting >700W silicon solutions.
• Implement high-speed routing and topologies to support signaling beyond 50GHz while minimizing loss and crosstalk.
• Collaborate with SI/PI engineers to define and meet signal and power integrity requirements.
• Optimize CoWoS (Chip-on-Wafer-on-Substrate) interposer and substrate designs for thermal and electrical performance.
• Perform DRC and LVS verification and maintain layout design documentation and guidelines.
• Coordinate with chip design, packaging, and OSAT/manufacturing teams to ensure manufacturability and yield.
• Support design reviews and provide technical guidance and mentorship to junior engineers.

Requirements

Must-have skills and experience for the role.

• 10+ years in IC substrate layout design for high-performance processors or accelerators.
• Hands-on experience with large substrate packages (>50mm) and complex high-density multi-layer layouts.
• Proven ability to design high-power package PDNs for >700W systems.
• Expertise in high-speed signaling design (>50GHz) and practical SI mitigation (crosstalk, reflections, impedance control).
• Strong experience with CoWoS/interposer integration and understanding of package-level impacts.
• Advanced proficiency with Allegro Package Designer (constraints, routing, design verification).
• Deep practical knowledge of SI/PI principles applied at the package level.
• Strong analytical ability, documentation practices, and experience working in cross-functional, fast-paced teams.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field (the posting specifies B.S./M.S. in EE, CE, or related).

About the Company

Company: Etched

Headquarters: San Jose, CA, United States

Etched develops purpose-built AI inference ASICs and systems optimized for transformer models, aiming to deliver significantly higher performance, lower cost, and lower latency than GPUs. The company focuses on enabling applications like real-time video generation and advanced reasoning agents, and is backed by leading investors and engineers.