Strategic Student Program — Functional Verification (FV) Applications Engineering Intern (Fall 2026)
SiemensJob Title
Strategic Student Program — Functional Verification (FV) Applications Engineering Intern (Fall 2026)
Role Summary
Short-term internship within Siemens Industry Software's Functional Verification applications engineering team. The intern will support technical sales engagements and develop demos/tutorials showcasing verification management tools and AI-enabled workflows.
This is an 8–10 week program (part-time or full-time) with preferred locations in Boston, MA or Phoenix, AZ and hybrid/remote options.
Experience Level
Entry-level internship targeted at current Master’s students. No specific years of professional experience required; suitable for students expected to graduate in 2026 or 2027.
Responsibilities
Primary tasks and deliverables for the internship.
- Support technical sales and customer engagements related to Siemens functional verification tools.
- Develop, document, and present a tutorial or demo that highlights verification management solutions and Agentic AI capabilities.
- Learn and apply verification methodologies, workflows, and related technologies.
- Contribute to internal documentation and possibly customer-facing materials.
- Work independently and collaboratively to solve technical problems and deliver assigned work on schedule.
Requirements
Concrete must-have skills and practical requirements. Educational items (degree, field, coursework, GPA, graduation window) are listed under Education Requirements below and omitted here to avoid duplication.
- Authorization to work in the U.S. without current or future sponsorship.
- Proficient with Microsoft Office (Word, Excel, PowerPoint).
- Familiarity with VSCode, Git, and Linux.
- Comfortable creating and delivering technical presentations to an engineering audience.
- Strong analytical, problem-solving, time-management, written and verbal communication skills.
- Self-motivated, proactive, able to work in a remote or hybrid setting.
Nice-to-have:
- Prior exposure to functional verification tools or verification workflows in a lab or project setting.
- Experience supporting technical sales or customer demos.
Education Requirements
Must be currently enrolled in a Master's program (Master’s degree required). Pursuing a Master’s in Electrical Engineering or Computer Science is specified. GPA 3.0+ required. Completed coursework or experience with Verilog, SystemVerilog, and VHDL and a solid understanding of hardware design and verification fundamentals are expected. Expected graduation in 2026 or 2027.
About the Company
Company: Siemens
Headquarters: Munich, Germany
Siemens EDA is a leading global provider of Electronic Design Automation (EDA) products and systems. Their innovative solutions enable companies to enhance the development of electronic products efficiently and effectively, keeping pace with the complex demands of technology and physics. Siemens is committed to delivering advanced workflow solutions that integrate both EDA and MCAD tools for multi-domain design and manufacturing in the semiconductor industry.
