Static Timing Analysis Methodology Engineer/Lead

Job Title

Static Timing Analysis Methodology Engineer/Lead

Role Summary

Lead development and maintenance of static timing analysis (STA) methodologies and flows for advanced digital designs. Work closely with design, CAD/DA, and characterization teams to ensure timing closure and robust, automated timing flows for FPGA products.

Hands-on work will include STA tool integration, timing model management, scripting, and development of automation and test infrastructure.

Experience Level

Senior — requires 8+ years of relevant industry experience in static timing analysis and methodology development.

Responsibilities

The role involves owning STA flows, improving timing methodology, and delivering tools and automation that teams use for timing closure.

• Develop, support, and maintain STA flows and automation.
• Collaborate on timing model creation, maintenance, and methodology improvements for .lib models.
• Integrate STA flows with CAD/DA toolchains and design teams to ensure reliable timing closure.
• Design, develop, test, and debug software tools and flows used in design automation.
• Capture requirements/user stories; write functional and test code; automate builds and deployments.
• Perform unit, integration, and end-to-end testing of tools and flows.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• Must-have: 8+ years of experience in static timing analysis and STA methodology/flow development.
• Must-have: 8+ years working with Liberty (.lib) model formats and timing models.
• Must-have: Strong scripting skills (Python, Perl, Tcl, shell).
• Must-have: Hands-on experience with STA tools such as Synopsys PrimeTime and Cadence Tempus.
• Preferred: Experience with Liberty model characterization and STA-tool-based Liberty extraction.
• Preferred: Familiarity with Fusion Compiler, Innovus, Cadence Pegasus, and other EDA tools.
• Preferred: Solid understanding of digital circuit design and simulation.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field is required per the posting; the role also specifies 8+ years of experience in the listed STA and methodology areas.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.