Staff Verification Design Engineer

Job Title

Staff Verification Design Engineer

Role Summary

Join the verification team to develop and execute verification strategies for digital, gate-level and analog/mixed-signal ASICs. Work with design engineers to ensure tape-out quality and support post-silicon bring-up and ATE validation.

Experience Level

Senior level. The posting requests 3+ years of semiconductor industry experience.

Responsibilities

Core duties include writing and running verification work, supporting tape-out, and improving verification infrastructure.

• Perform block and chip-level verification at RTL, gate-level and AMS.
• Run digital/mixed-signal simulations and formal verification.
• Define verification strategy and detailed verification plans with design teams.
• Develop tests, run regressions, and monitor coverage to meet tape-out quality goals.
• Participate in design/project reviews and provide verification-based schedule and priority input.
• Support post-silicon bring-up and debug for bench validation and automated test equipment (ATE).
• Improve verification scalability and portability via environment enhancements and tool automation.

Requirements

Must-have technical skills and professional attributes.

• 3+ years experience in the semiconductor industry.
• Hands-on experience with SystemVerilog as a verification language and UVM implementation.
• Ability to debug digital simulations at RTL and gate-level, isolating module- and system-level issues.
• Scripting experience in Python or Perl for automation and flow support.
• Clear understanding of ASIC design flow.
• Strong analytical, synthesis and problem-solving skills; independent and self-motivated with good teamwork.
• Excellent verbal and written communication skills.

Education Requirements

M.S. in Electrical Engineering, Computer Engineering, Computer Science or higher (explicitly listed). No alternative-equivalent language provided in the posting.

Desired Qualifications

Nice-to-have skills that improve fit:

• Experience setting up UVM verification environments from scratch.
• Familiarity with VHDL or SystemVerilog RNM.
• Experience automating verification flows with Python/Perl in industrial settings.
• Analog behavioral model development/verification experience.

About the Company

Company: Semtech

Headquarters: Camarillo, California, USA

Semtech Corporation is a high-performance semiconductor company providing IoT systems and Cloud connectivity solutions. The company focuses on delivering innovative technology solutions that support a smarter, more connected, and sustainable planet, with a dedication to quality across infrastructure, industrial, and consumer markets.