Staff Verification Applications Engineer

Job Title

Staff Verification Applications Engineer

Role Summary

Senior applications engineer working with customers to deploy and scale Synopsys VCS and Verdi simulation and debug tools into real verification flows for complex SoCs. The role combines customer-facing deployment, debugging of UVM/SystemVerilog environments, and collaboration with R&D to close product gaps.

Experience Level

Senior - the posting targets experienced engineers with approximately 5–12 years of hands-on verification or applications engineering experience.

Responsibilities

Primary responsibilities include field deployment, technical support, and validation of simulation/debug flows for customer tape-outs.

• Drive customer deployments and integrate VCS/Verdi into existing verification flows.
• Diagnose and resolve issues across UVM testbenches, SVA assertions, Low Power (UPF) flows, and gate-level timing simulations.
• Collaborate with global R&D and product teams to reproduce customer issues and influence the product roadmap.
• Lead competitive evaluations and benchmarks demonstrating simulation and debug advantages.
• Develop and maintain automation and flow scripts (Perl, Tcl, Python, Shell, Make).
• Support customers adopting AI-driven verification tools and advanced simulation features.
• Interface with customers across time zones and manage multiple concurrent engagements to production readiness.

Requirements

Must-have technical skills and domain experience. Preferences noted where applicable.

• Must-have: Strong working knowledge of VCS simulation technology and Verdi debug platform, or equivalent tools.
• Must-have: Deep expertise in SystemVerilog, UVM, and SVA applied to real RTL designs.
• Must-have: Proven experience with Low Power (UPF) flows and gate-level timing simulations in customer or validation environments.
• Must-have: Advanced scripting for automation and flow development (Perl, Tcl, Python, Shell, Make).
• Must-have: Solid understanding of digital design fundamentals, Verilog/VHDL, and UNIX/Linux environments.
• Nice-to-have: Exposure to DPI, C/C++, SystemC, functional safety practices, or GenAI verification tools.
• Nice-to-have: Experience running benchmarks and competitive evaluations for simulation performance.
• Willingness to travel for onsite customer engagements when required.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering or a related technical field. The posting expects 5–12 years of relevant verification or applications engineering experience; equivalent practical experience may be considered.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.