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Staff Systems Engineer, Architecture & Requirements

Neurophos
September 19, 2026
Full-time
On-site
Austin, Texas, United States
$185,000 - $215,000 USD yearly
SoC Architecture Jobs, Level - Senior

Job Title

Staff Systems Engineer, Architecture & Requirements

Role Summary

Lead the architecture and requirements effort for Neurophos's optical vector-matrix multiplication (OVMM) engine. Own the OVMM signal-path architecture, decompose product-level requirements into subsystem and interface specifications, and keep requirements coherent, leveled, and traceable across disciplines.

This is a hands-on systems role that translates product intent into defensible subsystem allocations, finds and resolves interface conflicts early, and drives architecture trade-offs across optics, analog, digital, and software teams.

Experience Level

Senior (Staff-level). The role expects 5+ years of relevant systems engineering, requirements management, or architecture experience for complex electro-optic, mixed-signal, or communications hardware.

Responsibilities

Primary and secondary responsibilities include specification, interface control, trade studies, and requirements management across disciplines.

  • Own and maintain the OVMM signal-path architecture and its consistency as designs evolve.
  • Translate product- and system-level requirements into leveled subsystem specifications and work packages with clear ownership and priorities.
  • Define and maintain interface specifications across optics, analog, digital, and software; identify and resolve interface conflicts early.
  • Lead architecture trade studies (channel counts, TX/RX configurations, aspect ratio, etc.) and quantify impacts on performance, power, and complexity.
  • Define and manage configuration and variant trades, maintaining traceability between requirements and product variants.
  • Run requirements reviews, negotiate scope with Responsible Engineers, and resolve conflicts before downstream propagation.
  • Collaborate with performance/modeling and calibration/bring-up teams to validate architecture choices and ensure verifiability.
  • Maintain requirements-management tooling, version-controlled specification repositories, and traceability artifacts.
  • Mentor engineers on requirements decomposition, specification discipline, and trade-study methodology.

Requirements

Must-have skills and experience required to perform the role; preferred skills listed separately.

  • 5+ years in systems engineering, requirements management, or architecture definition for complex electro-optic, mixed-signal, or communications hardware.
  • Proven ability to build and maintain leveled requirements sets, interface control documents, and verification/traceability matrices; flow top-level requirements into defensible subsystem allocations.
  • Ability to quantify architectural trade-offs (performance, power, complexity, cost) and defend decisions across disciplines.
  • Working fluency with signal-path and link-budget models (Python or MATLAB) sufficient to evaluate trade-study impact.
  • Excellent written and verbal communication; ability to negotiate and align priorities across engineers, functional leads, and executives.

Nice-to-have:

  • Experience with requirements-management tooling (DOORS, Jira) and Git-based, machine-readable specification repositories.
  • Familiarity with optical or RF communication systems and high-speed mixed-signal architecture.
  • Experience defining product configuration and variant management for complex hardware systems.
  • Exposure to formal gate-review processes (PDR/CDR) and familiarity with Cadence Virtuoso/Spectre for reviewing analog implementations.

Education Requirements

MS or PhD in Electrical Engineering, Applied Physics, or a closely related field with emphasis on systems engineering or mixed-signal/optical system architecture. (This posting specifies MS or PhD as the education expectation.)


About the Company

Company: Neurophos

Headquarters: Sunnyvale, California, United States

Startup developing silicon-photonic AI accelerator chips that use programmable metasurfaces and dense optical cells to perform matrix multiplications at the speed of light, targeting large-scale AI inference with much higher energy efficiency and performance than traditional electronic approaches.

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Date Posted: 2026-09-18