Staff System Validation Engineer (Post Silicon)
SiFiveRole Summary
As a RISC-V System Validation Engineer in the CoreIP team, you will be responsible for performing root cause analysis of SiFive cores on silicon. You will work closely with the System Software team to help in reproducing the issues reported by customers and facilitate internal debugging between HW and Software teams.
Experience Level
Mid-level
Responsibilities
Key responsibilities include:
- Owning system-level root cause analysis across processor, SoC, bootloaders, Linux kernel, board, and tools.
- Driving failure triage with customer silicon and decomposing ambiguous failures into testable hypotheses and structured debug plans.
- Working closely with the FPGA team to reproduce the failure in the emulation environment.
Requirements
Candidates should have the following qualifications:
- Solid understanding of SoC architectures and experience in chip bring-up or post-silicon verification.
- Deep understanding of Linux kernel internals relevant to silicon debug, including cold/warm bootup flow, boot flow, DRAM initialization, exception handling, and memory management.
- Experience with root cause analysis of failures at the processor boundary.
- Proficiency with core debugger (gdb required, T32 is a plus) and performance counters.
- Ability to correlate kernel logs, ftrace, perf, and crash dumps with hardware trace and performance counters.
Education Requirements
Not specified.
About the Company
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
