Staff STA Engineer

Job Title

Staff STA Engineer

Role Summary

Lead synthesis and static timing analysis (STA) for complex high-performance ICs with large digital and analog interfaces. Influence implementation, improve methodology, and lead small technical teams to drive timing and signoff quality.

Requires cross-functional collaboration and up to 10% travel. First shift / days.

Experience Level

Senior-level. 6–12 years of relevant experience with a proven track record of 4+ successful lower-geometry tapeouts.

Responsibilities

Deliver synthesis and STA tasks across RTL-to-GDS implementation and support physical design and signoff activities.

• Perform digital synthesis for high-performance blocks and manage DFT insertion and timing checks.
• Develop, validate, and debug timing constraints; perform RTL-to-netlist LEC and debug failures.
• Set up, converge, and optimize STA flows; manage multi-mode, multi-corner timing, noise, and timing-DRC signoff.
• Implement timing ECOs using tool-driven and manual techniques to achieve timing closure.
• Automate timing flows and analyses using Tcl/Perl/Python and enhance flows to resolve timing/timing-DRC issues.
• Support floor-planning, placement, CTS, routing, extraction, physical verification, EM/IR analysis, and signoff checks.
• Collaborate with designers and cross-functional teams to root-cause issues and propose practical solutions.

Requirements

Core technical skills and practical experience required for successful performance in this role.

• Hands-on experience in digital synthesis, STA, timing analysis, DFT modes, and signoff for complex high-speed SoC designs at advanced process nodes (16nm and below).
• Ability to develop complex timing constraints for IP, subsystem, and full-chip flows.
• Familiarity with commands and constructs across synthesis, STA, LEC, and PD tools.
• Strong analysis skills to root-cause timing violations and propose corrective actions across implementation stages.
• Proven experience with timing ECOs and leakage/dynamic power optimization during synthesis.
• Proficiency in scripting and automation (Tcl, Perl, Python) for timing analysis and flow automation.
• Experience with flow setup, convergence, reviews, and flow optimization.
• Experience with floor-planning, placement, CTS, routing, extraction, physical verification, and EM/IR flows is desirable.
• Good communication skills in cross-collaborative environments.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering preferred.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.