Staff / Sr. Staff DFT Solutions Engineer

Job Title

Staff / Sr. Staff DFT Solutions Engineer

Role Summary

Deliver end-to-end design-for-test (DFT) solutions for customer digital IC designs, from architecture planning and scan insertion through pattern generation, silicon bring-up, and diagnostics. Work directly with customers across complex SoC projects in automotive, AI, and consumer electronics to validate test methodologies and improve first-pass silicon success.

The role blends hands-on technical implementation, customer-facing design reviews and training, and prototyping of new DFT methodologies in collaboration with solution architects and R&D.

Experience Level

Senior-level. Typical experience: Bachelor's degree +7 years or Master's degree +5 years in relevant engineering fields (see Education Requirements for details).

Responsibilities

Key responsibilities include technical ownership of customer DFT engagements and methodology validation:

• Design and implement DFT architectures (scan, MBIST, IEEE 1687) and validate them for complex SoCs with multiple IP blocks.
• Perform scan insertion, ATPG pattern generation, and silicon bring-up diagnostics and failure analysis.
• Participate in customer design reviews to identify test-flow gaps and propose concrete improvements to increase coverage or reduce test time.
• Prototype and validate new DFT methodologies with internal teams before customer deployment.
• Provide technical support, training, and workshops to customer engineering teams; resolve hands-on issues during integration and bring-up.
• Conduct product demonstrations, competitive benchmarking, and evaluations to support account growth and product adoption.
• Analyze silicon test data, diagnose failures, and present actionable findings to customers and internal stakeholders.

Requirements

Technical skills and experience required or preferred.

Must-have:

• Hands-on experience with RTL coding, DFT insertion, ATPG pattern generation, and silicon bring-up for digital ICs.
• Deep knowledge of scan architectures, fault models, test access networks, and IEEE standards (1149.1, 1500, 1687).
• Proven ability to implement and validate scan solutions for large, multi‑IP SoCs with complex hierarchies and multiple clock domains.
• Strong written and verbal communication skills for technical explanation to engineering and non-technical stakeholders.
• Ability to manage multiple customer engagements and work independently on complex technical problems.

Nice-to-have:

• Experience with MBIST architecture planning and integration, especially in automotive or safety‑critical environments.
• Familiarity or exposure to Synopsys DFT tools such as TetraMAX, DFT Compiler, or MBIST Architect.
• Experience conducting methodology workshops and customer training.

Education Requirements

Bachelor's degree with 7+ years or Master's degree with 5+ years in Electronics Engineering, Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.