Staff SoC PD Engineer

Job Title

Staff SoC PD Engineer

Role Summary

Lead physical implementation and backend methodology for SoC and block-level designs on advanced FinFET nodes. Provide technical leadership across floorplanning, place-and-route, ECO, STA, timing and power closure, and physical verification.

Drive PD flow automation and Agentic AI integration, mentor engineers, and coordinate with foundry, EDA vendors, and senior stakeholders to achieve tape-out readiness.

Experience Level

Senior (Staff / Sr Staff). The role expects multi-year ASIC physical design experience; see Education Requirements for degree-linked minimums.

Responsibilities

Responsible for defining and executing physical design methodology, hands-on implementation, verification and cross-team coordination.

• Define and own backend design methodology for block and full-chip implementation.
• Lead floorplanning, place-and-route, ECO execution, STA, and timing/power closure across multiple complex blocks and full SoCs.
• Implement power optimization techniques (DVFS, multi-Vt, power domains) and support UPF/CPF flows.
• Drive physical verification and signoff (including LEC/timing analyses and addressing DRC/LVS concerns).
• Architect and implement large-scale back-end automation frameworks and flow infrastructure.
• Apply advanced simulation and analysis to optimize power, performance and area.
• Write and review technical documentation; present methodology and readiness assessments to senior management.
• Coordinate with foundry, EDA vendors, and cross-functional teams to resolve implementation and process issues.

Requirements

Key technical skills and practical experience required; degrees are listed under Education Requirements.

• Must-have: Several years of ASIC physical design experience including full-chip and block-level implementation, P&R, ECO, STA, timing/power closure, and physical verification.
• Must-have: Strong scripting and automation skills (Shell, Python, Tcl) and experience building scalable PD flow infrastructure.
• Must-have: Experience with power optimization techniques and power intent (UPF/CPF) implementation.
• Must-have: Proven ability to work independently, mentor engineers, and communicate technical decisions to senior leadership.
• Must-have: Experience interfacing with foundry and EDA vendors and managing complex tape-out risks.
• Nice-to-have: Experience applying AI/LLM-driven techniques or autonomous agents to EDA problems and optimization.
• Nice-to-have: Prior responsibility for defining organization-level PD methodology or leading PD teams.

Education Requirements

Bachelor's, Master's, or PhD in Science, Engineering, or related field were listed as minimum qualifications with experience thresholds: Bachelor's +4 years, Master’s +3 years, PhD +2 years of relevant ASIC physical design/ECO/STA/physical verification/power analysis experience. Preferred: Master’s in VLSI, Electrical/Electronic Engineering, Physics Engineering, Computer Engineering, or Computer Science. (Equivalent practical experience implied by degree-based combinations.)

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.