Staff SoC Integration and Performance Lead

Job Title

Staff SoC Integration and Performance Lead

Role Summary

Lead integration of verified Arm IP into SoC-level RTL platforms and drive early system-level performance analysis using RTL simulation and emulation. The role sits on Arm's SoC Performance Analysis Team within Central Technology and focuses on workload bring-up, firmware enablement, and performance bottleneck analysis to influence future SoC architectures.

Experience Level

Senior (Staff level). Years of experience not specified in the posting.

Responsibilities

The core responsibilities center on SoC RTL integration, platform bring-up, performance measurement, and cross-functional debug and leadership.

• Lead integration of functionally verified, performance-critical IP into SoC-level RTL platforms.
• Modify and stitch RTL components to build and evaluate multiple SoC configurations and architecture variants.
• Bring up SoC platforms in RTL simulation and emulation for early performance exploration.
• Implement incremental firmware changes to enable boot flow, workload execution, and test-case bring-up.
• Verify SoC functionality using bare-metal tests, benchmarks, and OS boot flows.
• Enable and debug performance workloads and benchmarks on simulation and emulation platforms.
• Analyze performance behavior across CPU, interconnect, memory subsystem, and key IP blocks to identify bottlenecks.
• Collaborate with architects to define and refine future SoC architecture choices.
• Drive cross-disciplinary debug of integration, firmware, workload, and performance issues.
• Provide technical leadership and mentorship to junior engineers and cross-functional partners.

Requirements

Must-have technical skills and experience required to perform the role.

• Strong understanding of computer and SoC architecture, memory subsystems, and bus/interconnect protocols.
• Hands-on experience integrating IP and bringing up full-chip SoC test cases in RTL simulation and/or emulation environments.
• Experience developing or modifying RTL using Verilog or SystemVerilog.
• Experience with SoC-level debug (reset, clock, memory map, interrupts, interconnect, firmware interactions).
• Experience enabling workloads, benchmarks, or bare-metal tests on RTL simulation and performance emulation platforms.
• Ability to analyze performance data and identify bottlenecks across SoC components.
• Strong problem-solving skills for hardware/software interaction issues and ability to drive debug across teams.
• Excellent communication, collaboration, and stakeholder-management skills; proactive leadership in ambiguous projects.

Nice-to-have:

• Proficiency with Unix/Linux environments, scripting, and source-control systems (Git/Subversion).
• Familiarity with Arm architecture and CPU instruction sets.
• Experience with boot firmware, low-level software, compilers, assemblers, or device drivers.
• Experience with performance workloads (SPEC, Geekbench, multimedia, memory bandwidth/latency benchmarks).
• Experience with emulation platforms, FPGA prototyping, or performance-analysis infrastructure.
• Familiarity with AMBA protocols (AXI, ACE, CHI, APB) and related interconnect technologies.
• Experience building automation, regression, dashboards, or debug workflows for large SoC projects.

Education Requirements

Not specified.

About the Company

Company: Arm

Headquarters: Cambridge, United Kingdom

ARM is a global leader in semiconductor and software design, driving innovation in computing technology. The company specializes in designing processors and systems that provide the essential building blocks for electronic devices. ARM's architecture is widely used in smartphones, servers, and IoT devices, and its collaborative culture fosters bold thinking, diversity, and high-impact benefits for its talented workforce.