Staff Silicon Photonics Design Engineer

Job Title

Staff Silicon Photonics Design Engineer

Role Summary

Senior silicon photonics designer responsible for end-to-end design, simulation, layout, and characterization of passive PIC components for a high-performance co-packaged optics system targeting AI inference. Works on compact, production-ready photonic designs and coordinates with foundries, VLSI, packaging, systems, and test teams.

Experience Level

Senior-level. Expectation: 3+ years of hands-on silicon photonics design experience in industry, or equivalent depth of graduate research with demonstrated tapeout and measurement record.

Responsibilities

Deliver photonic building blocks from concept through production, collaborate with cross-functional teams, and validate performance across process corners.

• Design, simulate, and optimize passive components: edge couplers, grating couplers, directional/hybrid couplers, waveguides, splitters, PSRs, crossings, and MMIs with targets for insertion loss, return loss, bandwidth, and polarization performance.
• Perform FDTD, EME, and circuit-level simulations (Lumerical, OptSim, or equivalents); run tolerance and process-corner analyses to maximize yield.
• Implement PIC layouts and generate DRC-clean GDS using Cadence Virtuoso, KLayout, or script-based parametric flows; manage DRC/LVS sign-off and mask data preparation.
• Plan and execute DOE and test-chip strategies; coordinate measurements to close the loop between simulation and silicon results.
• Manage tapeout processes with silicon photonics foundries and interface with foundry process engineers on design rules and process corners.
• Collaborate with VLSI, packaging, systems, and test teams to integrate PICs into broader co-packaged optics solutions.

Requirements

Key qualifications and technical skills required and preferred.

• Must-have: 3+ years of hands-on silicon photonics design experience in industry or equivalent research with tapeout and measurement evidence.
• Must-have: Proven expertise designing passive SOI photonic components (edge/grating couplers, waveguides, splitters, directional couplers, MMIs).
• Must-have: Proficiency with photonic simulation tools and solvers (FDTD, BPM, FDE, EME, CMT) such as Ansys Lumerical, Synopsys RSoft, Photon Design, or equivalents.
• Must-have: PIC layout experience (Cadence Virtuoso, KLayout, GDSFactory/IPKISS or equivalent) and familiarity with DRC/LVS flows and GDS generation.
• Must-have: Experience with at least one commercial silicon photonics foundry PDK and tapeout flow (TSMC, GlobalFoundries, Tower, AIM Photonics, etc.).
• Must-have: Programming skills in Python and/or MATLAB for simulation automation and data analysis.
• Must-have: Working knowledge of datacom or coherent transceiver link architectures and system-level optical specifications.
• Nice-to-have: Familiarity with electro-optic device design (lasers, MZM, ring modulators, Ge photodiodes), SiN platforms, optical packaging, automated measurement scripting, and experience with co-packaged optics or heterogeneous integration.

Education Requirements

M.S. or Ph.D. in Electrical Engineering, Photonics, Applied Physics, or a closely related discipline; or equivalent practical experience/research depth demonstrated by tapeout and measurement records.

About the Company

Company: Neurophos

Headquarters: Sunnyvale, California, United States

Startup developing silicon-photonic AI accelerator chips that use programmable metasurfaces and dense optical cells to perform matrix multiplications at the speed of light, targeting large-scale AI inference with much higher energy efficiency and performance than traditional electronic approaches.