Staff/Senior Staff Physical Design Floorplan & PDN Lead

Job Title

Staff/Senior Staff Physical Design Floorplan & PDN Lead

Role Summary

Lead chip-level floorplanning and power-delivery architecture for large-scale SoCs or sub-chips within the RTL-to-GDSII / Physical Implementation team. Own floorplan decisions and PDN strategies that balance power, performance, and area across the implementation flow.

Serve as the technical lead coordinating RTL/architecture trade-offs, sign-off teams, and methodology development to enable reliable high-performance tape-outs at advanced process nodes.

Experience Level

Senior (Staff / Senior Staff). 10–14 years of relevant physical-design experience, including multiple advanced-node tape-outs.

Responsibilities

The role focuses on architectural floorplanning, PDN design, IR/EM analysis, and cross-functional PPA trade-offs.

• Lead chip-level floorplanning: macro placement, pin assignment, partition definition for multi-million gate designs.
• Architect and implement Power Delivery Networks, specifying metal-stack usage and grid density to meet performance and reliability targets.
• Perform IR-drop (static/dynamic) and Electromigration analysis; diagnose root causes and define fixes that preserve timing.
• Collaborate with RTL and architecture teams to propose micro-architectural changes that improve physical outcomes (bus widths, pipeline stages, memory configuration).
• Develop and deploy automated flows and best practices for floorplanning and PDN synthesis across the implementation team.
• Mentor engineers, drive technical reviews, and present trade-offs to stakeholders.

Requirements

Concise list of must-have technical skills and experience; nice-to-have items follow.

Must-have

• 10+ years in Physical Design with multiple successful tape-outs at advanced nodes (7nm, 5nm, or 3nm).
• Proven expertise in PDN design and modeling, including complex power-up sequences and multi-voltage domains.
• Deep proficiency in hierarchical floorplanning and top-level integration using industry tools (Cadence Innovus or Synopsys IC Compiler II).
• Strong IR-drop and Electromigration analysis skills and the ability to propose architectural/physical mitigations.
• Understanding of thermal-aware PDN and high-current-density physical implications.
• Advanced scripting for automation and analysis (Tcl, Python, or Perl).
• Demonstrated ability to lead cross-functional PPA trade-offs and influence RTL/architecture decisions.

Nice-to-have

• Experience developing PDN synthesis methodology and automated flows for large teams.
• Prior leadership of floorplan/PDN efforts on complex multi-chip or multi-power-domain designs.

Education Requirements

B.Tech or M.Tech in Electrical / Electronic Engineering or equivalent practical experience.

About the Company

Company: EnCharge AI

EnCharge AI develops advanced AI hardware and software systems for edge-to-cloud computing, focusing on in-memory computing technology to deliver high compute efficiency and density with low power consumption. Founded in 2022, the company targets power-, energy-, and space-constrained applications with integrated hardware architectures and software stacks for scalable, reliable AI deployment.