Staff/Senior Staff Physical Design Engineer (Technical Lead)
EnCharge AIJob Title
Staff/Senior Staff Physical Design Engineer (Technical Lead)
Role Summary
Technical lead for physical design (PD) delivery of a major sub-chip or complex block. This is a player-coach role: you will both execute hands‑on PD tasks and provide technical direction, mentoring, and schedule ownership for a small team.
The role focuses on achieving aggressive PPA (Power, Performance, Area) targets, timing convergence, and full sign‑off readiness while coordinating across RTL, DFT, and synthesis teams.
Experience Level
Senior-level. Target experience ranges: Staff 8–10 years; Senior Staff 11–13 years.
Responsibilities
Lead PD delivery for critical, timing- or congestion-sensitive blocks and ensure project tape-out milestones are met.
- Provide technical leadership and workload management for a small PD team; mentor engineers and raise the technical bar.
- Take hands-on ownership of complex blocks/sub-chip partitions with highest risk for PPA and timing.
- Define and implement timing and PPA convergence strategies beyond standard vendor flows.
- Develop advanced Tcl and Python automation to improve flow efficiency, data mining, and sign-off reproducibility.
- Coordinate with RTL, DFT, and synthesis teams; communicate risks and drive left-shift optimizations.
- Ensure sign-off readiness across STA, EM/IR, and physical verification flows.
Requirements
Key must-have technical skills and experience for immediate contribution as a PD technical lead.
- 8–13 years PD experience with multiple successful lead-level tape-outs (Staff: 8–10 yrs; Senior Staff: 11–13 yrs).
- Expert-level proficiency in Cadence Innovus and Tempus.
- Deep Static Timing Analysis (STA) expertise, including complex clocking, multi-corner sign-off, and crosstalk closure.
- Proven PPA optimization at advanced nodes (7nm, 5nm or below) using custom floorplanning, CTS and convergence techniques.
- Advanced scripting skills in Tcl and Python to build scalable, repeatable methodologies and automation.
- Sign-off tool experience for EM/IR and physical verification (examples: Voltus/Apache, Pegasus/Calibre).
- Strong analytical problem-solving, assertive technical decision-making, and stakeholder management skills.
- Demonstrated mentorship and people-lead capabilities for small engineering teams.
Nice-to-have:
- Experience with SOC clocking, FEV/VCLP flows, or specialized low-power convergence techniques.
- Prior ownership of sub-chip partitioning and full-flow GDSII delivery.
Education Requirements
Not specified.
About the Company
Company: EnCharge AI
EnCharge AI develops advanced AI hardware and software systems for edge-to-cloud computing, focusing on in-memory computing technology to deliver high compute efficiency and density with low power consumption. Founded in 2022, the company targets power-, energy-, and space-constrained applications with integrated hardware architectures and software stacks for scalable, reliable AI deployment.
