Staff / Senior Staff NPI Debug Engineer

Job Title

Staff / Senior Staff NPI Debug Engineer

Role Summary

Senior individual contributor responsible for leading cross-functional debug taskforces to resolve critical new-product-introduction (NPI) silicon, hardware, and yield issues for FPGA programs. Focus areas include analog, mixed-signal, power delivery, and signal-integrity interactions across design, test, validation, and manufacturing.

The role is highly technical and requires hands-on hardware debug, yield analysis, and executive-level communication to drive recovery plans and mentor engineering teams.

Experience Level

Senior-level; typically requires 6+ years of relevant experience.

Responsibilities

Lead critical investigations and coordinate debug activities across multiple engineering and manufacturing teams.

• Lead and coordinate cross-functional debug taskforces ("tiger teams") for critical NPI blockers, especially those involving analog, power, or signal integrity.
• Develop fault trees, designs of experiments (DOEs), and parallel investigation plans; assign ownership across Design, Product, Test, Validation, and Manufacturing.
• Aggregate and synthesize data from simulation/circuit analysis, ATE/test data, failure analysis, and yield signatures to identify root causes.
• Maintain dashboards, run taskforce syncs, and present findings, recovery schedules, and risk assessments to executive leadership.
• Lead yield analysis activities (pareto, parametric shift, tester correlation, statistical review) and drive corrective actions across foundry, assembly, test, and design.
• Influence test program development, diagnostic coverage, and outlier detection screening to prevent escapes.
• Define and guide experimental builds; validate engineering fixes and direct failure analysis methodologies.

Requirements

Must-have skills and experience (required); preferred items listed separately.

• 6+ years experience in hardware debug, NPI engineering, product/yield engineering, or system validation.
• 6+ years leading technical taskforces to resolve critical silicon, hardware, or yield issues under tight schedules.
• 6+ years driving yield analysis and yield improvement for semiconductor, FPGA, SoC, or complex hardware products.
• 6+ years data analysis experience using Python, JMP, or equivalent tools.
• Hands-on experience with lab equipment, fault isolation, and failure analysis tools and methodologies.
• Strong technical communication and crisis-management skills; able to translate multidisciplinary debug data into clear risk assessments and action plans for leadership.
• Ability to synthesize complex datasets and define actionable debug strategies.

Education Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, or a related technical field is required. Master’s degree or PhD in Electrical Engineering, Electronics, Physics, or a related field is preferred.

Preferred / Nice-to-have

Additional experience that strengthens a candidate:

• Strong background in analog and mixed-signal debug.
• Familiarity with fault isolation (FI) and failure analysis (FA) techniques.

Compensation

Bay Area salary range (annual): $149,100 - $215,000 USD. Actual pay may vary by location, experience, and other factors.