Staff/Senior Staff Engineer, STA

Job Title

Staff/Senior Staff Engineer, STA

Role Summary

Responsible for driving static timing analysis (STA) and timing closure for block-level and full-chip SoC designs. Works within the VLSI design team and partners with RTL, synthesis, CTS, physical design, and signoff teams to achieve tapeout-ready timing signoff.

Tasks include developing and validating timing constraints, performing pre- and post-layout timing analysis across MMMC corners, debugging violations, and implementing ECOs to reach timing convergence.

Experience Level

Senior-level; 7–13 years of hands-on STA and timing closure experience.

Responsibilities

Primary responsibilities include:

• Perform block-level and full-chip STA across modes and MMMC corners.
• Analyze and debug setup, hold, recovery, removal, clock gating, and signal-integrity-related timing violations.
• Develop, validate, and maintain timing constraints (SDC) and timing exceptions.
• Drive timing closure through ECO implementation, timing optimization, and convergence activities.
• Perform pre-layout and post-layout timing analysis and support tapeout signoff requirements.
• Assess timing impact of process, voltage, and temperature (PVT) variations using variation-aware methodologies.
• Review and validate timing exceptions including false paths, multicycle paths, case analysis, and clock definitions.
• Participate in cross-functional design reviews and provide guidance on timing-related issues.
• Generate timing reports, closure metrics, and signoff summaries for stakeholders.
• Support STA methodology improvements, automation, and best practices.

Requirements

Must-have skills and experience:

• 7–13 years of practical STA and timing closure experience for block-level and/or full-chip designs.
• Strong understanding of CMOS fundamentals and end-to-end semiconductor design flow.
• Experience with setup/hold analysis, path-based analysis (PBA), and timing signoff methodologies.
• Knowledge of OCV, AOCV, POCV, timing derates, uncertainty modeling, and MMMC analysis.
• Deep understanding of clock tree concepts including latency, skew, jitter, uncertainty, and propagation.
• Experience developing and debugging timing constraints and timing exceptions (false paths, multicycle paths, generated clocks).
• Hands-on experience with STA tools such as Synopsys PrimeTime and/or Cadence Tempus.
• Strong scripting and automation skills (Tcl, Perl, Python, or similar).
• Analytical debugging skills and effective cross-functional communication.

Nice-to-have:

• Experience with low-power timing analysis and UPF/CPF-aware STA methodologies.
• Familiarity with SI-aware timing, crosstalk analysis, and IR-drop-aware timing closure.
• Exposure to advanced technology nodes, variation-aware signoff, and automation/flow development.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, VLSI, Microelectronics, or a related field.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.