Staff RTL Design Engineer - CPU LS/PF/MMU
SiFiveJob Title
Staff RTL Design Engineer - CPU LS/PF/MMU
Role Summary
Design microarchitecture and RTL for high-performance RISC-V CPU cores, with emphasis on load-store unit, prefetch, and virtual memory/MMU functionality. Work on a cross-functional CPU team responsible for delivering configurable processor IP to market.
The role covers microarchitecture development, RTL implementation, integration with verification and physical design, and clear technical documentation.
Experience Level
Senior (Staff-level). The posting specifies 3+ years of design experience; equivalent industry experience is acceptable.
Responsibilities
Primary responsibilities include designing CPU features, integrating with tool frameworks, and coordinating verification and physical implementation.
- Architect, design, and implement CPU features, performance improvements, and ISA extensions using Chisel and RTL.
- Integrate design content into the Chisel/FIRRTL framework and improve automation for documentation, verification testbenches, and software packaging.
- Perform initial sandbox verification and collaborate with verification teams to develop and execute verification plans.
- Work with physical implementation and performance modeling teams to meet frequency, area, power, and performance targets.
- Produce and maintain microarchitecture specifications and documentation; share knowledge across the team.
Requirements
Must-have technical skills and experience. Education requirements are listed below under Education Requirements.
- 3+ years of CPU design experience.
- Academic or professional experience with CPU RTL design.
- Proficiency in Verilog, SystemVerilog, or VHDL.
- Strong software engineering practices, including functional programming concepts and test-driven development; ability to write adaptive unit tests.
- Good verification principles, including SVA and coverage awareness.
- Ability to work effectively in a collaborative engineering team.
Nice-to-have:
- Experience with Scala/Chisel, Bluespec, or other hardware-generation DSLs.
- Knowledge of the RISC-V instruction set architecture.
- Expertise in out-of-order microarchitecture areas such as load-store units, coherent caches, prefetching, or MMU/TLBs.
- Familiarity with Git/GitHub, Jira, and Confluence.
Education Requirements
BS or MS in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field; or equivalent practical experience.
About the Company
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
