Staff RTL Design Engineer - Cache Subsystem

Job Title

Staff RTL Design Engineer - Cache Subsystem

Role Summary

Design and deliver high-performance, energy-efficient cache subsystems for SiFive's RISC-V CPU core products. The role spans microarchitecture, RTL implementation, verification coordination, and close collaboration with physical implementation and performance teams to meet frequency, area, power, and performance targets.

This position is based in Hsinchu, Taiwan and requires authorization to work in Taiwan and successful export-control clearance where applicable.

Experience Level

Senior-level. The posting requests at least five years of relevant industry experience working on high-performance cache subsystem design.

Responsibilities

Primary responsibilities include microarchitecting cache subsystems, implementing RTL, and working across teams to verify and deliver silicon-quality IP.

• Architect, design and implement new high-performance cache subsystems and enhance existing cache IP.
• Define microarchitecture and produce clear specifications and documentation.
• Perform initial sandbox verification and collaborate with verification teams to create and execute detailed test plans.
• Work with physical implementation teams to optimize for frequency, area, and power.
• Collaborate with performance modeling teams for exploration and optimization to meet performance goals.
• Support IP through integration toward tapeout and silicon bring-up.

Requirements

Must-have skills and experience required for successful performance in the role.

• Minimum ~5 years industry experience on high-performance, energy-efficient cache subsystem designs, ideally within CPU or GPU subsystems.
• Proven track record of cache subsystem development from architecture through to tapeout.
• Expertise in multi-level coherent cache architectures and designs.
• Experience with TileLink or similar interconnect architectures.
• Proficiency in RTL design using Verilog, SystemVerilog or VHDL.
• Strong attention to detail and commitment to high-quality design.
• Effective collaborator; able to work across microarchitecture, verification, physical implementation, and performance teams.

Nice-to-have:

• Knowledge of RISC-V architecture.
• Experience with Scala and/or Chisel.
• Familiarity with IP verification methodologies and tools such as UVM and Formal.
• Experience with object-oriented and/or functional programming languages.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline, or equivalent practical industry experience.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.