Staff QA Engineer (DDR, CXL, PCIE)

Job Title

Staff QA Engineer (DDR, CXL, PCIE)

Role Summary

Join the management subsystem and interconnect validation team responsible for QA of PCIe, CXL, memory controller and firmware products. The role focuses on developing automation, authoring tests in Python and C/C++, validating protocol compliance and performance, and integrating quality checks into CI/CD pipelines.

Experience Level

Senior - requires several years of hands-on QA/validation experience (posting indicates 4–10 years).

Responsibilities

Core responsibilities include test development, automation, and cross-team validation.

• Develop and modify tests using Pytest and GTest frameworks.
• Write unit and integration tests from scratch for Python and C/C++ modules.
• Debug failed tests, automation issues, and analyze firmware logs.
• Integrate and run automated tests within CI/CD pipelines; work with Jenkins/GitLab CI/GitHub Actions.
• Set up protocol analyzers, capture and analyze traces for protocol compliance and performance validation.
• Use automation and AI-assisted techniques to generate test scenarios when applicable.
• Collaborate with cross-functional engineering teams and lead QA/validation efforts for releases.

Requirements

Must-have technical skills and experience; nice-to-have items listed separately.

• 4–10 years of hands-on QA/validation and leadership experience for PCIe, CXL and firmware; understanding of DDR.
• Strong knowledge of PCIe, CXL and NVMe protocols, SSD architecture, and firmware testing practices.
• Proficiency in Python and C/C++ and ability to create tests in both languages.
• Experience with Pytest and GTest; proficiency with Robot Framework and scripting is expected.
• Practical experience debugging automation, analyzing firmware logs, and troubleshooting test failures.
• Experience integrating automated tests into CI/CD workflows (Jenkins, GitLab CI, GitHub Actions).
• Solid OOP knowledge and software design principles.
• Ability to set up and use protocol analyzers, capture traces, and perform trace analysis.
• Strong communication and collaboration skills; experience mentoring or leading validation efforts.

Nice-to-have:

• Experience with high-speed interconnects, storage benchmarking, and advanced CI/CD integration.
• Understanding of management protocols such as MCTP, Redfish, NVMe-MI.

Education Requirements

BS or MS degree in Computer Science, Computer Engineering, or Electrical Engineering.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.