Staff / Principal Engineer - Multi-Die Advanced TechPPA Methodology & Automation

Job Title

Staff / Principal Engineer - Multi-Die Advanced TechPPA Methodology & Automation

Role Summary

Lead methodology and automation work to enable technology PPA (performance, power, area) for sub-2nm and future process nodes, with emphasis on multi-die and 2.5D/3D implementations. Collaborate with architecture, IP, physical design, DTCO, foundry, EDA, and packaging teams to translate technology capabilities into production-ready flows.

Experience Level

Senior (Staff/Principal). Years of experience not specified.

Responsibilities

Deliver methodology, automation, and cross-functional enablement to optimize technology-node PPA and support production execution.

• Drive technology PPA enablement for sub-2nm and future process nodes focusing on performance, power, area, utilization, routability, and convergence.
• Develop scalable methodologies and automation to evaluate trade-offs across libraries, memories, routing resources, power delivery, clocking, design rules, and implementation constraints.
• Analyze PPA limiters including congestion, IR/EM, thermal, timing, leakage, dynamic power, and physical verification closure.
• Enable multi-die and 2.5D/3D implementations where package, power, and thermal trades affect PPA.
• Build AI-assisted automation and analytics for PPA exploration, recipe optimization, debugging, and closure.
• Partner with IP, DTCO, foundry, EDA, architecture, and implementation teams to identify and close technology entitlement gaps.
• Convert technology learnings into repeatable flows, checks, dashboards, and sign-off readiness criteria for production.
• Provide hands-on execution and technical leadership to deliver results.

Requirements

Must-have technical skills and experience.

• Strong expertise in advanced-node SoC physical implementation and technology PPA optimization.
• Deep understanding of technology-node trade-offs: libraries, memories, routing, utilization, power delivery, clocking, congestion, timing, leakage, dynamic power, and physical verification constraints.
• Programming and scripting skills (Python, C); experience with EDA tools, version control (Git), and distributed processing/debug environments.
• Hands-on experience with low-power design methodologies, UPF-based design, chip finishing, and physical verification flows in advanced process technologies.
• Proven ability to lead technical initiatives and collaborate with internal teams, foundries, and EDA providers.
• Strong problem-solving, communication, and collaboration skills for global teamwork.

Nice-to-have:

• Deep knowledge of advanced clocking structures, power-delivery optimization, and physical verification convergence techniques.
• Familiarity with AI-assisted design automation and methodology optimization flows.

Education Requirements

Not specified.

About the Company

Company: Arm

Headquarters: Cambridge, United Kingdom

ARM is a global leader in semiconductor and software design, driving innovation in computing technology. The company specializes in designing processors and systems that provide the essential building blocks for electronic devices. ARM's architecture is widely used in smartphones, servers, and IoT devices, and its collaborative culture fosters bold thinking, diversity, and high-impact benefits for its talented workforce.