Staff / Principal Engineer - Multi-Die Advanced Tech PPA Methodology & Automation

Job Title

Staff / Principal Engineer - Multi-Die Advanced Tech PPA Methodology & Automation

Role Summary

Senior engineering role within Solutions Engineering focused on enabling technology PPA (performance, power, area) for advanced nodes including sub-2nm and multi-die systems. The role coordinates across architecture, IP, physical implementation, foundry, EDA and packaging teams to translate technology capabilities into production-ready methodologies, automation, and flows.

Experience Level

Senior-level engineer. Specific years of experience not stated; role expects demonstrated technical leadership and ownership of cross-functional initiatives.

Responsibilities

Deliver methodology, automation, and cross-functional enablement to optimize PPA and production readiness for advanced-node and multi-die designs.

• Drive technology PPA enablement for sub-2nm and future nodes, focusing on performance, power, area, utilization, routability and convergence.
• Develop scalable methodologies and automation to evaluate and optimize tradeoffs across libraries, memories, routing, power delivery, clocking and design rules.
• Analyze and mitigate PPA limiters: congestion, IR/EM, thermal, timing, leakage, dynamic power and verification closure.
• Enable multi-die and 2.5D/3D implementations where package, power and thermal tradeoffs affect PPA.
• Execute hands-on delivery and demonstrate measurable improvements in implementation outcomes.
• Build AI-assisted automation and analytics for PPA exploration, recipe optimization, debug and closure.
• Partner with IP, DTCO, foundry, EDA, architecture and implementation teams to identify entitlement gaps and drive improvements.
• Convert technology learnings into repeatable flows, checks, dashboards and sign-off criteria for production execution.

Requirements

Must-have technical skills and experience required to perform the role.

• Strong expertise in advanced-node SoC physical implementation and methodology development focused on technology PPA optimization.
• Deep understanding of technology-node tradeoffs: libraries, memories, routing, utilization, power delivery, clocking, congestion, timing, leakage and physical verification constraints.
• Proficient programming and scripting skills (Python, C), familiarity with EDA tool flows, version control (Git) and distributed processing/debug environments.
• Hands-on experience with low-power design methodologies, UPF-based design, chip finishing and physical verification in advanced process technologies.
• Proven ability to lead technical initiatives and collaborate with internal teams, foundries, EDA providers and ecosystem partners.
• Strong problem-solving, communication and collaboration skills for globally distributed teams.

Nice-to-have:

• Deep knowledge of advanced clocking structures, power-delivery optimization and verification convergence techniques.
• Familiarity with AI-assisted design automation and methodology optimization flows.

Education Requirements

Not specified.

About the Company

Company: Arm

Headquarters: Cambridge, United Kingdom

ARM is a global leader in semiconductor and software design, driving innovation in computing technology. The company specializes in designing processors and systems that provide the essential building blocks for electronic devices. ARM's architecture is widely used in smartphones, servers, and IoT devices, and its collaborative culture fosters bold thinking, diversity, and high-impact benefits for its talented workforce.