Staff/Principal Engineer - HBM Design for Test (DFT)

Job Title

Staff/Principal Engineer - HBM Design for Test (DFT)

Role Summary

The Staff/Principal Engineer leads DFT architecture and implementation for HBM core and base die, with primary focus on logic-die MBIST support, test architecture, and program-level specification ownership. The role partners with design, verification, and physical implementation teams to ensure scalable, manufacturable test solutions across HBM families.

Experience Level

Senior; typically 5+ years of relevant experience in design-for-test, logic test, or SoC/ASIC design roles.

Responsibilities

Primary responsibilities include technical ownership of DFT solutions and cross-functional program support.

• Define, implement, and document logic-die MBIST architectures: controller interaction, access mechanisms, sequencing, and broadcast behavior.
• Own test definitions and DFT entry flows supporting MBIST, logic test, interface test, and debug modes (including customer modes).
• Ensure DFT features are integrated, scalable, and generation-extensible with logic and SoC architects.
• Support RTL debug and functional verification for DFT/MBIST features using Verilog and simulation tools.
• Specify checks, assertions, and coverage expectations for logic-die test functionality.
• Collaborate with APR/physical teams on timing closure, clocking/reset evaluation, scan/MBIST routing, and tradeoffs for congestion, power, and area.
• Provide guidance on DFT-friendly floorplanning and high-fanout/broadcast test structures; supply scripts to improve implementation efficiency.
• Support late-stage implementation and signoff debugging related to DFT timing, connectivity, or integration issues.
• Act as DFT/MBIST point of contact for assigned programs; contribute to documentation, training, and mentorship of junior engineers.

Requirements

Must-have technical experience and skills.

• Proven experience in design-for-test and logic test methodologies, including MBIST fundamentals and memory/logic test concepts.
• Working knowledge of memory architectures; HBM or DRAM experience preferred.
• Experience influencing DFT requirements, specifications, and verification expectations across organizations.
• Hands-on experience with Verilog and simulation tools for RTL/DFT feature verification and debug.
• Ability to collaborate cross-functionally with architects, verification, and physical implementation teams.
• Strong written and verbal communication skills; ability to document and disseminate technical decisions.
• Preferred: exposure to IEEE 1500 / DFT access mechanisms / broadcast test concepts and experience supporting first-silicon or high-volume manufacturing debug.

Education Requirements

Bachelor's degree in Electrical Engineering or a related field is required; Master’s degree preferred. (No equivalent-experience statement provided.)

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.