Staff Physical Verification Engineer

Job Title

Staff Physical Verification Engineer

Role Summary

Responsible for end-to-end physical verification (PV) signoff of advanced SoC/ASIC designs, owning block-to-full-chip checks through final tape-out. Works with place-and-route, analog/mixed-signal, timing, reliability and CAD teams to ensure first-time-right silicon.

Leads PV methodology and execution for DRC, LVS, PERC, ESD and related reliability checks and serves as the technical interface to foundry and EDA vendors.

Experience Level

Senior — typically 8–12 years' experience in physical verification for complex ASIC/SoC designs, with multiple production tape-outs and signoff ownership.

Responsibilities

Primary responsibilities include:

• Own full-chip and block-level PV signoff (DRC, LVS, ERC, PERC, ANT/ESD) and deliver clean GDS for tape-out.
• Manage PV schedules, track violations, and drive convergence to signoff-acceptable error levels.
• Develop, maintain and optimize PV flows and automation scripts (Calibre, ICV, etc.).
• Define and enhance PERC and reliability checks (ESD, EOS, EM, current-density, point-to-point resistance).
• Influence floorplanning and power-grid planning to reduce late-stage PV iterations.
• Debug complex DRC/LVS/PERC violations including FinFET-specific, multi-patterning, and corner-case connectivity issues.
• Validate and qualify new nodes, rule decks, and DFM/fill flows with CAD and process teams.
• Mentor engineers on PV best practices, root-cause analysis, and signoff criteria.
• Act as primary technical contact to foundry and EDA vendors for PV and reliability issues and waivers.

Requirements

Must-have technical skills and experience:

• 8–12 years of hands-on PV experience for complex ASIC/SoC designs, including signoff ownership on production tape-outs.
• Demonstrated signoff ownership for at least one 5 nm or sub-7 nm production tape-out in a FinFET process.
• Deep experience with industry PV tools (Siemens Calibre, Synopsys ICV/IC Validator) for DRC/LVS/ERC/PERC/ANT/ESD.
• Experience integrating Cadence Virtuoso with PV tools for DRC/LVS/PERC flows.
• Strong scripting skills (Python, Perl, Tcl, or Unix shell) for automation and flow development.
• Experience with PERC-based reliability flows (ESD, EOS, LUP, current-density checks) and signoff criteria.
• Familiarity with DFM/DFY checks, density/fill strategies, and pattern-matching rule decks.
• Solid understanding of physical design (place & route, timing closure, power integrity) and its interaction with PV signoff.
• Proven problem-solving, debugging and cross-functional communication skills.
• Willingness to travel up to 10% as required.

Education Requirements

Bachelor's or Master’s degree in Electrical/Electronics Engineering or a related technical field.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.