Staff Physical Verification Engineer

Job Title

Staff Physical Verification Engineer

Role Summary

Lead full-chip physical verification (PV) signoff for advanced SoC/ASIC designs, owning DRC, LVS, PERC and related reliability checks from block-level verification through final tape-out.

Work cross-functionally with place-and-route, analog/mixed-signal, timing analysis and CAD teams to define PV methodology, resolve violations, and deliver first-time-right silicon.

Experience Level

Senior — typically 8–12 years of hands-on physical verification experience for complex ASIC/SoC designs, including signoff ownership on production tape-outs.

Responsibilities

Primary technical and execution ownership for PV signoff and related activities.

• Own full-chip and block-level signoff (DRC, LVS, ERC, PERC, ANT/ESD) for multiple complex SoCs.
• Manage PV schedules, track violations, and drive convergence to signoff-acceptable results for tape-out readiness.
• Develop, maintain, and optimize PV flows and automation (e.g., Calibre, ICV) for performance and robustness.
• Define and enhance PERC and reliability checks (ESD, EOS, EM, current-density, point-to-point resistance) in collaboration with reliability and I/O teams.
• Own floorplanning and power-grid planning to reduce PV iterations and avoid late-stage violations.
• Debug complex DRC/LVS/PERC issues including corner-case connectivity, device recognition, FinFET rules, multi-patterning, and EUV constraints.
• Validate and qualify new technology nodes, rule decks, and fill/DFM flows with CAD and foundry partners.
• Mentor engineers on PV best practices, root-cause analysis, and signoff criteria.
• Serve as primary technical interface to foundry and EDA vendors for PV and reliability issues and waivers.

Requirements

Must-have technical skills and practical experience for immediate contribution to advanced-node PV signoff.

• Proven hands-on expertise with industry-standard PV tools (e.g., Siemens Calibre, Synopsys ICV) for DRC, LVS, ERC, PERC and ANT/ESD checks.
• Experience with Cadence Virtuoso-PV integration (Virtuoso layout to Calibre/ICV) for DRC/LVS/PERC flows.
• Proven experience owning DRC/LVS/PERC signoff on at least one 5 nm or sub-7 nm production tape-out in a FinFET process.
• Strong knowledge of advanced process-node rule challenges, FinFET-specific constraints, multi-patterning and EUV implications.
• Solid scripting and automation skills in one or more: Python, Perl, Tcl, or Unix shell.
• Experience with PERC-based reliability flows for ESD, EOS, LUP and current-density checks, including setup and signoff criteria definition.
• Familiarity with DFM/DFY checks, density/fill strategies, and pattern-matching-driven rule decks.
• Strong understanding of physical design (place & route, timing closure, power integrity) and its interaction with PV signoff.
• Excellent problem-solving, debug, and cross-functional communication skills; demonstrated ability to lead technical closure.
• Willingness to travel approximately 10% as required.

Education Requirements

Bachelor's or Master's degree in Electrical/Electronics Engineering or a related technical field.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.