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Staff Physical Design Engineer - Top-Level Timing & STA

Technology Navigators
July 02, 2026
Full-time
On-site
San Jose, California, United States
Physical Design Jobs, Level - Senior

Job Title

Staff Physical Design Engineer β€” Top-Level Timing & STA

Role Summary

Lead full-chip static timing analysis (STA) and timing signoff for advanced-node SoCs (5nm / 3nm / 2nm). Drive MMMC timing closure, develop and maintain timing constraints and hierarchical timing budgets, and coordinate with RTL, Physical Design, and Clocking teams to deliver tapeout-ready timing results.

Experience Level

Senior / Staff level β€” typically 7+ years of experience in STA, timing closure, and signoff for advanced semiconductor processes.

Responsibilities

Primary responsibilities focus on end-to-end STA ownership, timing closure, and signoff for complex SoCs.

  • Own full-chip STA across all modes and PVT corners and lead final timing signoff.
  • Drive MMMC timing closure and convergence across hierarchical flows.
  • Develop and maintain timing constraints and hierarchical timing budgets.
  • Analyze setup/hold violations and execute ECOs to achieve closure.
  • Assess crosstalk/SI and OCV/AOCV/POCV impacts on timing.
  • Execute signoff using industry-standard tools and improve signoff methodologies for runtime and convergence.
  • Collaborate with RTL, Physical Design, and Clock teams to debug top-level timing issues and improve QoR.
  • Present timing closure status, risks, and mitigation plans to leadership.

Requirements

Key technical must-haves and useful additions.

  • Must-have: Proven experience owning full-chip STA, MMMC closure, timing ECOs, and signoff for complex SoCs.
  • Must-have: Strong skills in timing constraint development and hierarchical timing budgeting.
  • Must-have: Practical experience with crosstalk/SI analysis and OCV / AOCV / POCV considerations.
  • Must-have: Hands-on experience with Synopsys PrimeTime (PT / PT-SI) and Cadence Tempus.
  • Must-have: Experience with advanced nodes (5nm, 3nm, 2nm).
  • Must-have: Scripting proficiency in Tcl and Python; Perl experience preferred.
  • Nice-to-have: Track record improving signoff methodologies, runtime, and convergence efficiency.
  • Nice-to-have: Strong cross-functional leadership and communication for multi-team integration.

Education Requirements

Not specified.


About the Company

Company: Technology Navigators

Headquarters: Austin, TX, USA

Technical staffing firm based in Austin, Texas, specializing in recruiting skilled technologists for project-oriented consulting and contract positions since 1999.

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Date Posted: 2026-07-02