Staff Physical Design Engineer: CPU Implementation & Flow Automation
SiFiveJob Title
Staff Physical Design Engineer: CPU Implementation & Flow Automation
Role Summary
Lead development and maintenance of the RTL-to-GDS implementation flow for high-performance CPU cores, focusing on PPA (Power, Performance, Area) closure on advanced FinFET process nodes. The role combines hands-on physical implementation, flow automation, and deployment of ML-enhanced methodologies.
Collaborate with methodology, IP, and design teams to produce production-ready recipes and troubleshoot tool or flow issues across design iterations.
Experience Level
Senior level. The posting requests 7+ years of experience in Physical Design/Methodology with a focus on high-performance digital implementation.
Responsibilities
Primary responsibilities include developing implementation recipes, driving PPA closure, deploying ML-based optimization, and automating flows for repeatable results.
- Develop, validate, and deploy production-ready RTL-to-GDS recipes using Synopsys Fusion Compiler.
- Drive block-level and hierarchical PPA closure using timing-driven placement, CTS, and routing techniques.
- Deploy ML optimization tools (e.g., DSO.ai) for automated design-space exploration and PPA improvement.
- Provide first-line technical support for flow and tool issues; collaborate with the methodology team to resolve bottlenecks.
- Work with IP teams (SRAM/standard cells) to characterize and model PPA impacts on the flow.
- Create and maintain robust Tcl/Python automation for flow customization and data analysis.
Requirements
Must-have technical skills and constraints for the role.
Must-have:
- 7+ years of experience in Physical Design/Methodology, focused on high-performance digital implementation.
- Proven experience with FinFET nodes (N5/N3) and practical understanding of N2/GAAFET challenges considered a plus.
- Expert proficiency with Synopsys digital implementation tools (Fusion Compiler, ICC2, PrimeTime, StarRC).
- Strong understanding of hierarchical physical design: floorplanning, pin assignment, timing budgeting.
- High proficiency in Tcl and Python for flow customization, automation, and data analysis.
- Demonstrated track record of resolving complex timing and congestion issues in high-speed, high-density CPU blocks.
- Ability to pass background and reference checks and provide proof of right to work in India.
- Willingness/ability to obtain any required export-control authorization or licenses if not already authorized.
Nice-to-have:
- Prior experience deploying ML-driven optimization tools (DSO.ai or similar) in production flows.
- Experience specifically with advanced node PPA optimization techniques and hierarchical signoff flows.
Education Requirements
Not specified.
About the Company
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
