Staff Physical Design Engineer

Job Title

Staff Physical Design Engineer

Role Summary

Lead EM and IR-drop analysis and signoff activities to ensure robust power delivery, signal integrity, and long-term reliability for high-performance ICs. Work within the silicon team across RTL, physical design, extraction, and analysis to implement power grid strategies that optimize performance, power, and area at advanced process nodes.

Hybrid role supporting Tenstorrent's RISC-V CPU and AI chip development; collaborative, delivery-focused engineering position.

Experience Level

Senior. Typical expectation: 7+ years of experience in physical design or signoff with a focus on EM/IR analysis; final level will be determined during interviews.

Responsibilities

Primary responsibilities include EMIR analysis, power-grid implementation, and signoff across hierarchical chip flows.

• Lead EM and IR-drop simulations and signoff (pre- and post-layout) to validate power delivery and EM compliance.
• Develop and implement power grid strategies to optimize performance, power, and area (PPA) at advanced nodes.
• Work with RTL, physical design, extraction, and analysis teams to identify and remediate IR/EM issues.
• Create and maintain signoff and waiver methodologies across block and chip hierarchies.
• Perform layout extraction, RC modeling, metal density checks, and impact analysis for IR and EM mitigation.
• Support integration of EMIR signoff into fast-paced chip design cycles and document analysis workflows.

Requirements

Clear separation of must-have and nice-to-have qualifications.

Must-have

• 7+ years of experience in physical design or signoff with a focus on EMIR analysis.
• Hands-on experience with RedHawk, Voltus, or equivalent industry-standard EMIR tools.
• Strong knowledge of IR-drop mitigation, electromigration compliance, and power grid design.
• Proficiency with layout extraction flows, RC modeling, and metal density verification.
• Experience working at advanced nodes (7nm, 5nm, 3nm).
• Scripting experience (TCL, Python, Perl, or Shell) to automate flows and analysis.
• Familiarity with floorplanning, bump/RDL considerations, and sign-off flows (DRC/LVS, timing closure).
• Ability to collaborate across RTL, PD, packaging, and reliability teams.
• Must be able to comply with U.S. export control requirements; employment may be contingent on citizenship/permanent residency documentation or export licensing.

Nice-to-have

• Experience with hierarchical EMIR methodology and waiver processes across chip hierarchies.
• Background in packaging-level analysis, reliability engineering, or AI/high-performance CPU design.
• Prior work integrating EMIR signoff into aggressive PPA-driven design flows.

Education Requirements

Not specified.

About the Company

Company: Tenstorrent

Headquarters: Austin, Texas, United States

Tenstorrent is a technology company focused on designing innovative computing solutions. They are known for their expertise in the development of advanced hardware, including ASICs and SoCs, aimed at enhancing performance and efficiency in various applications.