Staff Physical Design Engineer

Job Title

Staff Physical Design Engineer

Role Summary

The Staff Physical Design Engineer owns complex block- and/or top-level physical implementation for advanced-node SoCs and provides technical leadership to a small group of physical design engineers.

Responsibilities include driving implementation quality and on-time delivery across floorplanning, power planning, placement, CTS, routing, signoff, and physical verification for advanced technology nodes.

Experience Level

Senior — typically 8–12+ years of professional experience in physical design or equivalent demonstrated mastery.

Responsibilities

Key responsibilities include hands-on implementation, methodology development, and team enablement:

• Own end-to-end physical implementation for complex blocks or subsystems (floorplanning, power planning, placement, CTS, routing, ECO).
• Drive timing closure, congestion resolution, IR/EM mitigation, signal integrity, and physical verification to meet PPA and quality targets.
• Define and refine hierarchical PNR strategies, IO/PG structures, and SoC integration guidelines.
• Analyze and debug tool issues, timing failures, and physical anomalies; propose robust, scalable fixes.
• Develop and maintain physical design methodologies, scripts, and automated flows for PDN, clocking, exception handling, and signoff.
• Evaluate EDA tool capabilities and collaborate with CAD/enablement to adopt best practices.
• Provide technical direction, review designs, and mentor junior engineers to improve team capability.
• Collaborate with RTL, STA, DFT, CAD, and packaging teams; represent physical design in reviews and communicate risks and trade-offs.

Requirements

Must-have technical skills, experience, and expectations:

• Extensive hands-on experience in physical design for complex digital SoCs; proven record closing timing-, IR-, and congestion-critical blocks/subsystems.
• Familiarity with industry-standard PNR and signoff tools (examples: Cadence Innovus, Synopsys ICC2, PrimeTime/Tempus, RedHawk, Voltus).
• Strong knowledge of floorplanning, partitioning strategies, power grid and PDN methodology, IR/EM mitigation, and advanced clock tree/clock mesh design.
• Proficient with STA constraint formulation (modes/corners, exceptions, derates) and physical verification checks (DRC/LVS/antenna) and reliability considerations.
• Demonstrated problem-solving and debugging skills with a bias toward scalable, automated solutions.
• Clear written and verbal communication; experience mentoring and enabling team members.
• Willingness to travel as required (approximately 10%).

Nice-to-have:

• Experience on advanced process nodes (22nm, 16nm, 7nm, 5nm, 4nm).
• Prior experience defining SoC-level integration guidelines or IO/PG ring architectures.

Education Requirements

Not specified.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.